| Message ID | 20201026115530.304-1-jiangyifei@huawei.com |
|---|---|
| Headers | show |
| Series | Support RISC-V migration | expand |
On Tue, Oct 27, 2020 at 11:47 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 10/26/20 4:55 AM, Yifei Jiang wrote: > > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); > > This is truncating mstatus to target_ulong, i.e. breaking the output for > riscv32. You should use PRIx64 and print the whole 64-bit value. That is what we want to do though. For RV32 the mstatus CSR is only 32-bits, where the upper 32-bit are stored in mstatush (the top 32-bits of QEMU's internal mstatus). Alistair > > > r~ >
On 10/26/20 4:55 AM, Yifei Jiang wrote: > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); This is truncating mstatus to target_ulong, i.e. breaking the output for riscv32. You should use PRIx64 and print the whole 64-bit value. r~
On Mon, Oct 26, 2020 at 4:58 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. > This patch expands mstatus and vsstatus to uint64_t instead of > target_ulong so that it can be saved as one unit and reduce some > ifdefs in the code. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 8 +++++--- > target/riscv/cpu.h | 24 +++++++++++------------- > target/riscv/cpu_bits.h | 19 ++++--------------- > target/riscv/cpu_helper.c | 35 +++++++---------------------------- > target/riscv/csr.c | 18 ++++++++++-------- > target/riscv/op_helper.c | 11 ++++------- > 6 files changed, 41 insertions(+), 74 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f457..dd05a220c7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -216,13 +216,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); > #ifndef CONFIG_USER_ONLY > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); > #ifdef TARGET_RISCV32 > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", > + (target_ulong)(env->mstatus >> 32)); > #endif > if (riscv_has_ext(env, RVH)) { > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", > + (target_ulong)env->vsstatus); > } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de275782e6..e430670b60 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -140,14 +140,14 @@ struct CPURISCVState { > target_ulong resetvec; > > target_ulong mhartid; > - target_ulong mstatus; > + /* > + * For RV32 this is 32-bit mstatus and 32-bit mstatush. > + * For RV64 this is a 64-bit mstatus. > + */ > + uint64_t mstatus; > > target_ulong mip; > > -#ifdef TARGET_RISCV32 > - target_ulong mstatush; > -#endif > - > uint32_t miclaim; > > target_ulong mie; > @@ -179,16 +179,17 @@ struct CPURISCVState { > uint64_t htimedelta; > > /* Virtual CSRs */ > - target_ulong vsstatus; > + /* > + * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. > + * For RV64 this is a 64-bit vsstatus. > + */ > + uint64_t vsstatus; > target_ulong vstvec; > target_ulong vsscratch; > target_ulong vsepc; > target_ulong vscause; > target_ulong vstval; > target_ulong vsatp; > -#ifdef TARGET_RISCV32 > - target_ulong vsstatush; > -#endif > > target_ulong mtval2; > target_ulong mtinst; > @@ -200,10 +201,7 @@ struct CPURISCVState { > target_ulong scause_hs; > target_ulong stval_hs; > target_ulong satp_hs; > - target_ulong mstatus_hs; > -#ifdef TARGET_RISCV32 > - target_ulong mstatush_hs; > -#endif > + uint64_t mstatus_hs; > > target_ulong scounteren; > target_ulong mcounteren; > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index bd36062877..daedad8691 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -4,10 +4,10 @@ > #define TARGET_RISCV_CPU_BITS_H > > #define get_field(reg, mask) (((reg) & \ > - (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) > -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ > - (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ > - (target_ulong)(mask))) > + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) > +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ > + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ > + (uint64_t)(mask))) > > /* Floating point round mode */ > #define FSR_RD_SHIFT 5 > @@ -381,19 +381,8 @@ > #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ > #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ > #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ > -#if defined(TARGET_RISCV64) > #define MSTATUS_GVA 0x4000000000ULL > #define MSTATUS_MPV 0x8000000000ULL > -#elif defined(TARGET_RISCV32) > -#define MSTATUS_GVA 0x00000040 > -#define MSTATUS_MPV 0x00000080 > -#endif > - > -#ifdef TARGET_RISCV32 > -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) > -#else > -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) > -#endif > > #define MSTATUS64_UXL 0x0000000300000000ULL > #define MSTATUS64_SXL 0x0000000C00000000ULL > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 904899054d..109ee4bad6 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -110,27 +110,19 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) > > void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > { > - target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; > + uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | > + MSTATUS64_UXL; > bool current_virt = riscv_cpu_virt_enabled(env); > > g_assert(riscv_has_ext(env, RVH)); > > -#if defined(TARGET_RISCV64) > - mstatus_mask |= MSTATUS64_UXL; > -#endif > - > if (current_virt) { > /* Current V=1 and we are about to change to V=0 */ > env->vsstatus = env->mstatus & mstatus_mask; > env->mstatus &= ~mstatus_mask; > env->mstatus |= env->mstatus_hs; > > -#if defined(TARGET_RISCV32) > - env->vsstatush = env->mstatush; > - env->mstatush |= env->mstatush_hs; > -#endif > - > env->vstvec = env->stvec; > env->stvec = env->stvec_hs; > > @@ -154,11 +146,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > env->mstatus &= ~mstatus_mask; > env->mstatus |= env->vsstatus; > > -#if defined(TARGET_RISCV32) > - env->mstatush_hs = env->mstatush; > - env->mstatush |= env->vsstatush; > -#endif > - > env->stvec_hs = env->stvec; > env->stvec = env->vstvec; > > @@ -720,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > if (riscv_has_ext(env, RVH) && env->priv == PRV_M && > access_type != MMU_INST_FETCH && > get_field(env->mstatus, MSTATUS_MPRV) && > - MSTATUS_MPV_ISSET(env)) { > + get_field(env->mstatus, MSTATUS_MPV)) { > riscv_cpu_set_two_stage_lookup(env, true); > } > > @@ -781,7 +768,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > if (riscv_has_ext(env, RVH) && env->priv == PRV_M && > access_type != MMU_INST_FETCH && > get_field(env->mstatus, MSTATUS_MPRV) && > - MSTATUS_MPV_ISSET(env)) { > + get_field(env->mstatus, MSTATUS_MPV)) { > riscv_cpu_set_two_stage_lookup(env, false); > } > > @@ -844,7 +831,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > RISCVCPU *cpu = RISCV_CPU(cs); > CPURISCVState *env = &cpu->env; > bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); > - target_ulong s; > + uint64_t s; > > /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide > * so we mask off the MSB and separate into trap type and cause. > @@ -969,19 +956,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) > if (riscv_cpu_virt_enabled(env)) { > riscv_cpu_swap_hypervisor_regs(env); > } > -#ifdef TARGET_RISCV32 > - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, > - riscv_cpu_virt_enabled(env)); > - if (riscv_cpu_virt_enabled(env) && tval) { > - env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); > - } > -#else > env->mstatus = set_field(env->mstatus, MSTATUS_MPV, > - riscv_cpu_virt_enabled(env)); > + riscv_cpu_virt_enabled(env)); > if (riscv_cpu_virt_enabled(env) && tval) { > env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); > } > -#endif > > mtval2 = env->guest_phys_fault_addr; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index aaef6c6f20..e33f6cdc11 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -446,8 +446,8 @@ static int validate_vm(CPURISCVState *env, target_ulong vm) > > static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) > { > - target_ulong mstatus = env->mstatus; > - target_ulong mask = 0; > + uint64_t mstatus = env->mstatus; > + uint64_t mask = 0; > int dirty; > > /* flush tlb on mstatus fields that affect VM */ > @@ -480,19 +480,20 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) > #ifdef TARGET_RISCV32 > static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) > { > - *val = env->mstatush; > + *val = env->mstatus >> 32; > return 0; > } > > static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) > { > - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { > + uint64_t valh = (uint64_t)val << 32; > + uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; > + > + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { > tlb_flush(env_cpu(env)); > } > > - val &= MSTATUS_MPV | MSTATUS_GVA; > - > - env->mstatush = val; > + env->mstatus = (env->mstatus & ~mask) | (valh & mask); > > return 0; > } > @@ -1105,7 +1106,8 @@ static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) > > static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) > { > - env->vsstatus = val; > + uint64_t mask = (target_ulong)-1; > + env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; > return 0; > } > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 9b9ada45a9..e0b45e5eb7 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -79,7 +79,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, > > target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) > { > - target_ulong prev_priv, prev_virt, mstatus; > + uint64_t mstatus; > + target_ulong prev_priv, prev_virt; > > if (!(env->priv >= PRV_S)) { > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > @@ -148,18 +149,14 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) > riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > } > > - target_ulong mstatus = env->mstatus; > + uint64_t mstatus = env->mstatus; > target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); > - target_ulong prev_virt = MSTATUS_MPV_ISSET(env); > + target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); > mstatus = set_field(mstatus, MSTATUS_MIE, > get_field(mstatus, MSTATUS_MPIE)); > mstatus = set_field(mstatus, MSTATUS_MPIE, 1); > mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); > -#ifdef TARGET_RISCV32 > - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0); > -#else > mstatus = set_field(mstatus, MSTATUS_MPV, 0); > -#endif > env->mstatus = mstatus; > riscv_cpu_set_mode(env, prev_priv); > > -- > 2.19.1 > >
On Mon, Oct 26, 2020 at 4:58 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > This patches supported RISC-V migration based on tcg accel. And we have > verified related migration features such as snapshot and live migration. > > A few weeks ago, we submitted RFC patches about supporting RISC-V migration > based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html. > And we found that tcg accelerated migration can be supported with a few > changes. Most of the devices have already implemented the migration > interface, so, to achieve the tcg accelerated migration, we just need to > add vmstate of both cpu and sifive_plic. > > changes since v3 > 1. Apply Alistair's patch to exend get/set_field(): > https://www.mail-archive.com/qemu-devel@nongnu.org/msg753575.html > 2. Remake the patch: Merge m/vsstatus and m/vsstatush into one uint64_t > unit. > > Changes since v2: > 1. Move vmstate_riscv_cpu declaration to internals.h. > 2. Merge m/vsstatus and m/vsstatush into one uint64_t unit. > > Changes since v1: > 1. Add license head to target/riscv/machine.c. > 2. Regenerate some state of PMP at post_load hook. > > Yifei Jiang (6): > target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit > target/riscv: Add basic vmstate description of CPU > target/riscv: Add PMP state description > target/riscv: Add H extension state description > target/riscv: Add V extension state description > target/riscv: Add sifive_plic vmstate Thanks! Applied to riscv-to-apply.next Alistair > > hw/intc/sifive_plic.c | 26 ++++- > hw/intc/sifive_plic.h | 1 + > target/riscv/cpu.c | 16 ++-- > target/riscv/cpu.h | 24 +++-- > target/riscv/cpu_bits.h | 19 +--- > target/riscv/cpu_helper.c | 35 ++----- > target/riscv/csr.c | 18 ++-- > target/riscv/internals.h | 4 + > target/riscv/machine.c | 196 ++++++++++++++++++++++++++++++++++++++ > target/riscv/meson.build | 3 +- > target/riscv/op_helper.c | 11 +-- > target/riscv/pmp.c | 29 +++--- > target/riscv/pmp.h | 2 + > 13 files changed, 290 insertions(+), 94 deletions(-) > create mode 100644 target/riscv/machine.c > > -- > 2.19.1 > >