| Message ID | 1599712262-8819-3-git-send-email-hector.yuan@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
Hi, Rob sir: Sorry to bother you, may I have your review comment for the binding part? Appreciated. On Thu, 2020-09-10 at 12:31 +0800, Hector Yuan wrote: > From: "Hector.Yuan" <hector.yuan@mediatek.com> > > Add devicetree bindings for MediaTek HW driver. > > Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com> > --- > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > new file mode 100644 > index 0000000..118a163 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek's CPUFREQ Bindings > + > +maintainers: > + - Hector Yuan <hector.yuan@mediatek.com> > + > +description: > + CPUFREQ HW is a hardware engine used by MediaTek > + SoCs to manage frequency in hardware. It is capable of controlling frequency > + for multiple clusters. > + > +properties: > + compatible: > + const: "mediatek,cpufreq-hw" > + > + reg: > + minItems: 1 > + maxItems: 2 > + description: | > + Addresses and sizes for the memory of the HW bases in each frequency domain. > + > + reg-names: > + items: > + - const: "freq-domain0" > + - const: "freq-domain1" > + description: | > + Frequency domain name. i.e. > + "freq-domain0", "freq-domain1". > + > + "#freq-domain-cells": > + const: 1 > + description: | > + Number of cells in a freqency domain specifier. > + > + mtk-freq-domain: > + maxItems: 1 > + description: | > + Define this cpu belongs to which frequency domain. i.e. > + cpu0-3 belong to frequency domain0, > + cpu4-6 belong to frequency domain1. > + > +required: > + - compatible > + - reg > + - reg-names > + - "#freq-domain-cells" > + > +examples: > + - | > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x000>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x100>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x200>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x300>; > + }; > + > + cpu4: cpu@4 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x400>; > + }; > + > + cpu5: cpu@5 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x500>; > + }; > + > + cpu6: cpu@6 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x600>; > + }; > + > + cpu7: cpu@7 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x700>; > + }; > + }; > + > + /* ... */ > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpufreq_hw: cpufreq@11bc00 { > + compatible = "mediatek,cpufreq-hw"; > + reg = <0 0x11bc10 0 0x8c>, > + <0 0x11bca0 0 0x8c>; > + reg-names = "freq-domain0", "freq-domain1"; > + #freq-domain-cells = <1>; > + }; > + }; > + > + > + > +
On Tue, 2020-09-22 at 14:28 -0600, Rob Herring wrote: > On Thu, Sep 10, 2020 at 12:31:02PM +0800, Hector Yuan wrote: > > From: "Hector.Yuan" <hector.yuan@mediatek.com> > > > > Add devicetree bindings for MediaTek HW driver. > > > > Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com> > > --- > > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++ > > 1 file changed, 141 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > new file mode 100644 > > index 0000000..118a163 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > @@ -0,0 +1,141 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek's CPUFREQ Bindings > > + > > +maintainers: > > + - Hector Yuan <hector.yuan@mediatek.com> > > + > > +description: > > + CPUFREQ HW is a hardware engine used by MediaTek > > + SoCs to manage frequency in hardware. It is capable of controlling frequency > > + for multiple clusters. > > + > > +properties: > > + compatible: > > + const: "mediatek,cpufreq-hw" > > Needs to be SoC specific. This stuff is never constant from one SoC to > the next. 'cpufreq' is a Linuxism. What's the block called in the > datasheet? Use that. > OK, will use mediatek,sspm-dvfs-mt6779 instead. > Don't need quotes either. > OK, will remove it. > > + > > + reg: > > + minItems: 1 > > + maxItems: 2 > > + description: | > > + Addresses and sizes for the memory of the HW bases in each frequency domain. > > + > > + reg-names: > > + items: > > + - const: "freq-domain0" > > + - const: "freq-domain1" > > Kind of pointless to have names based on the index. Drop 'reg-names'. > OK, will drop it. > > + description: | > > + Frequency domain name. i.e. > > + "freq-domain0", "freq-domain1". > > + > > + "#freq-domain-cells": > > + const: 1 > > + description: | > > + Number of cells in a freqency domain specifier. > > You don't need this. It's not a common binding that's going to vary. > OK, will remove it. > > + > > + mtk-freq-domain: > > + maxItems: 1 > > + description: | > > + Define this cpu belongs to which frequency domain. i.e. > > + cpu0-3 belong to frequency domain0, > > + cpu4-6 belong to frequency domain1. > > This property doesn't go in the 'mediatek,cpufreq-hw' node. You would > need a separate schema. However, I think the easiest thing to do here is > something like this: > > mediatek,freq-domain-0 = <&cpu0>, <&cpu1>; > Sorry, may I know the reason and the details about how to separate schema? Thank you very much. The numbers of frequency domain may be vary from different projects. If I do the easier way, I may need to implement extra loop to check how many frequency domain. > Or you could just re-use the OPP binding with just 0 entries: > > opp-table-0 { > compatible = "mediatek,hw-operating-points", "operating-points-v2"; > }; > opp-table-1 { > compatible = "mediatek,hw-operating-points", "operating-points-v2"; > }; > In previous review stage, already abandon OPP framework in driver code. Will check with Viresh to see if its OK to add OPP back. > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - "#freq-domain-cells" > > + > > +examples: > > + - | > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 0>; > > + reg = <0x000>; > > + }; > > + > > + cpu1: cpu@1 { > > Unit address is wrong. > OK, will modify to "cpu1 : cpu@100" if we still decide to put freq_domain in CPU node. > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 0>; > > + reg = <0x100>; > > + }; > > + > > + cpu2: cpu@2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 0>; > > + reg = <0x200>; > > + }; > > + > > + cpu3: cpu@3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 0>; > > + reg = <0x300>; > > + }; > > + > > + cpu4: cpu@4 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 1>; > > + reg = <0x400>; > > + }; > > + > > + cpu5: cpu@5 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a55"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 1>; > > + reg = <0x500>; > > + }; > > + > > + cpu6: cpu@6 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a75"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 1>; > > + reg = <0x600>; > > + }; > > + > > + cpu7: cpu@7 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a75"; > > + enable-method = "psci"; > > + mtk-freq-domain = <&cpufreq_hw 1>; > > + reg = <0x700>; > > + }; > > + }; > > + > > + /* ... */ > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpufreq_hw: cpufreq@11bc00 { > > + compatible = "mediatek,cpufreq-hw"; > > + reg = <0 0x11bc10 0 0x8c>, > > + <0 0x11bca0 0 0x8c>; > > + reg-names = "freq-domain0", "freq-domain1"; > > + #freq-domain-cells = <1>; > > + }; > > + }; > > + > > + > > + > > + > > -- > > 1.7.9.5
On Wed, 2020-09-23 at 21:10 +0800, Hector Yuan wrote: > On Tue, 2020-09-22 at 14:28 -0600, Rob Herring wrote: > > On Thu, Sep 10, 2020 at 12:31:02PM +0800, Hector Yuan wrote: > > > From: "Hector.Yuan" <hector.yuan@mediatek.com> > > > > > > Add devicetree bindings for MediaTek HW driver. > > > > > > Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com> > > > --- > > > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++ > > > 1 file changed, 141 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > > new file mode 100644 > > > index 0000000..118a163 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > > @@ -0,0 +1,141 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek's CPUFREQ Bindings > > > + > > > +maintainers: > > > + - Hector Yuan <hector.yuan@mediatek.com> > > > + > > > +description: > > > + CPUFREQ HW is a hardware engine used by MediaTek > > > + SoCs to manage frequency in hardware. It is capable of controlling frequency > > > + for multiple clusters. > > > + > > > +properties: > > > + compatible: > > > + const: "mediatek,cpufreq-hw" > > > > Needs to be SoC specific. This stuff is never constant from one SoC to > > the next. 'cpufreq' is a Linuxism. What's the block called in the > > datasheet? Use that. > > > OK, will use mediatek,sspm-dvfs-mt6779 instead. > > Don't need quotes either. > > > OK, will remove it. > > > + > > > + reg: > > > + minItems: 1 > > > + maxItems: 2 > > > + description: | > > > + Addresses and sizes for the memory of the HW bases in each frequency domain. > > > + > > > + reg-names: > > > + items: > > > + - const: "freq-domain0" > > > + - const: "freq-domain1" > > > > Kind of pointless to have names based on the index. Drop 'reg-names'. > > > OK, will drop it. > > > + description: | > > > + Frequency domain name. i.e. > > > + "freq-domain0", "freq-domain1". > > > + > > > + "#freq-domain-cells": > > > + const: 1 > > > + description: | > > > + Number of cells in a freqency domain specifier. > > > > You don't need this. It's not a common binding that's going to vary. > > > OK, will remove it. > > > + > > > + mtk-freq-domain: > > > + maxItems: 1 > > > + description: | > > > + Define this cpu belongs to which frequency domain. i.e. > > > + cpu0-3 belong to frequency domain0, > > > + cpu4-6 belong to frequency domain1. > > > > This property doesn't go in the 'mediatek,cpufreq-hw' node. You would > > need a separate schema. However, I think the easiest thing to do here is > > something like this: > > > > mediatek,freq-domain-0 = <&cpu0>, <&cpu1>; > > > Sorry, may I know the reason and the details about how to separate > schema? Thank you very much. > Actually, I referenced the thermal-cooling-devices and send my yaml for review. https://elixir.bootlin.com/linux/v5.9-rc6/source/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml It used cpu node for cooling device, and thermal schema use it. Appreciated for any details. > The numbers of frequency domain may be vary from different projects. If > I do the easier way, I may need to implement extra loop to check how > many frequency domain. > > Or you could just re-use the OPP binding with just 0 entries: > > > > opp-table-0 { > > compatible = "mediatek,hw-operating-points", "operating-points-v2"; > > }; > > opp-table-1 { > > compatible = "mediatek,hw-operating-points", "operating-points-v2"; > > }; > > > In previous review stage, already abandon OPP framework in driver code. > Will check with Viresh to see if its OK to add OPP back. > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - reg-names > > > + - "#freq-domain-cells" > > > + > > > +examples: > > > + - | > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 0>; > > > + reg = <0x000>; > > > + }; > > > + > > > + cpu1: cpu@1 { > > > > Unit address is wrong. > > > OK, will modify to "cpu1 : cpu@100" if we still decide to put > freq_domain in CPU node. > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 0>; > > > + reg = <0x100>; > > > + }; > > > + > > > + cpu2: cpu@2 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 0>; > > > + reg = <0x200>; > > > + }; > > > + > > > + cpu3: cpu@3 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 0>; > > > + reg = <0x300>; > > > + }; > > > + > > > + cpu4: cpu@4 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 1>; > > > + reg = <0x400>; > > > + }; > > > + > > > + cpu5: cpu@5 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a55"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 1>; > > > + reg = <0x500>; > > > + }; > > > + > > > + cpu6: cpu@6 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a75"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 1>; > > > + reg = <0x600>; > > > + }; > > > + > > > + cpu7: cpu@7 { > > > + device_type = "cpu"; > > > + compatible = "arm,cortex-a75"; > > > + enable-method = "psci"; > > > + mtk-freq-domain = <&cpufreq_hw 1>; > > > + reg = <0x700>; > > > + }; > > > + }; > > > + > > > + /* ... */ > > > + > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + cpufreq_hw: cpufreq@11bc00 { > > > + compatible = "mediatek,cpufreq-hw"; > > > + reg = <0 0x11bc10 0 0x8c>, > > > + <0 0x11bca0 0 0x8c>; > > > + reg-names = "freq-domain0", "freq-domain1"; > > > + #freq-domain-cells = <1>; > > > + }; > > > + }; > > > + > > > + > > > + > > > + > > > -- > > > 1.7.9.5 >
Hi, Viresh & Rob Sir:
I will change frequency domain to below and define it in cpufreq_hw
schema rather than cpu node.
mediatek,freq-domain-0 = <&cpu0>, <&cpu1>;
Is it OK to you?
Or you think OPP define is a better solution?
opp-table-0 {
compatible = "mediatek,hw-operating-points", "operating-points-v2";
};
Thank you for the opinions.
On Wed, 2020-09-23 at 21:10 +0800, Hector Yuan wrote:
> On Tue, 2020-09-22 at 14:28 -0600, Rob Herring wrote:
> > On Thu, Sep 10, 2020 at 12:31:02PM +0800, Hector Yuan wrote:
> > > From: "Hector.Yuan" <hector.yuan@mediatek.com>
> > >
> > > Add devicetree bindings for MediaTek HW driver.
> > >
> > > Signed-off-by: Hector.Yuan <hector.yuan@mediatek.com>
> > > ---
> > > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++
> > > 1 file changed, 141 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> > > new file mode 100644
> > > index 0000000..118a163
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
> > > @@ -0,0 +1,141 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: MediaTek's CPUFREQ Bindings
> > > +
> > > +maintainers:
> > > + - Hector Yuan <hector.yuan@mediatek.com>
> > > +
> > > +description:
> > > + CPUFREQ HW is a hardware engine used by MediaTek
> > > + SoCs to manage frequency in hardware. It is capable of controlling frequency
> > > + for multiple clusters.
> > > +
> > > +properties:
> > > + compatible:
> > > + const: "mediatek,cpufreq-hw"
> >
> > Needs to be SoC specific. This stuff is never constant from one SoC to
> > the next. 'cpufreq' is a Linuxism. What's the block called in the
> > datasheet? Use that.
> >
> OK, will use mediatek,sspm-dvfs-mt6779 instead.
> > Don't need quotes either.
> >
> OK, will remove it.
> > > +
> > > + reg:
> > > + minItems: 1
> > > + maxItems: 2
> > > + description: |
> > > + Addresses and sizes for the memory of the HW bases in each frequency domain.
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: "freq-domain0"
> > > + - const: "freq-domain1"
> >
> > Kind of pointless to have names based on the index. Drop 'reg-names'.
> >
> OK, will drop it.
> > > + description: |
> > > + Frequency domain name. i.e.
> > > + "freq-domain0", "freq-domain1".
> > > +
> > > + "#freq-domain-cells":
> > > + const: 1
> > > + description: |
> > > + Number of cells in a freqency domain specifier.
> >
> > You don't need this. It's not a common binding that's going to vary.
> >
> OK, will remove it.
> > > +
> > > + mtk-freq-domain:
> > > + maxItems: 1
> > > + description: |
> > > + Define this cpu belongs to which frequency domain. i.e.
> > > + cpu0-3 belong to frequency domain0,
> > > + cpu4-6 belong to frequency domain1.
> >
> > This property doesn't go in the 'mediatek,cpufreq-hw' node. You would
> > need a separate schema. However, I think the easiest thing to do here is
> > something like this:
> >
> > mediatek,freq-domain-0 = <&cpu0>, <&cpu1>;
> >
> Sorry, may I know the reason and the details about how to separate
> schema? Thank you very much.
>
> The numbers of frequency domain may be vary from different projects. If
> I do the easier way, I may need to implement extra loop to check how
> many frequency domain.
> > Or you could just re-use the OPP binding with just 0 entries:
> >
> > opp-table-0 {
> > compatible = "mediatek,hw-operating-points", "operating-points-v2";
> > };
> > opp-table-1 {
> > compatible = "mediatek,hw-operating-points", "operating-points-v2";
> > };
> >
> In previous review stage, already abandon OPP framework in driver code.
> Will check with Viresh to see if its OK to add OPP back.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - reg-names
> > > + - "#freq-domain-cells"
> > > +
> > > +examples:
> > > + - |
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + cpu0: cpu@0 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 0>;
> > > + reg = <0x000>;
> > > + };
> > > +
> > > + cpu1: cpu@1 {
> >
> > Unit address is wrong.
> >
> OK, will modify to "cpu1 : cpu@100" if we still decide to put
> freq_domain in CPU node.
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 0>;
> > > + reg = <0x100>;
> > > + };
> > > +
> > > + cpu2: cpu@2 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 0>;
> > > + reg = <0x200>;
> > > + };
> > > +
> > > + cpu3: cpu@3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 0>;
> > > + reg = <0x300>;
> > > + };
> > > +
> > > + cpu4: cpu@4 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 1>;
> > > + reg = <0x400>;
> > > + };
> > > +
> > > + cpu5: cpu@5 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a55";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 1>;
> > > + reg = <0x500>;
> > > + };
> > > +
> > > + cpu6: cpu@6 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a75";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 1>;
> > > + reg = <0x600>;
> > > + };
> > > +
> > > + cpu7: cpu@7 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a75";
> > > + enable-method = "psci";
> > > + mtk-freq-domain = <&cpufreq_hw 1>;
> > > + reg = <0x700>;
> > > + };
> > > + };
> > > +
> > > + /* ... */
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + cpufreq_hw: cpufreq@11bc00 {
> > > + compatible = "mediatek,cpufreq-hw";
> > > + reg = <0 0x11bc10 0 0x8c>,
> > > + <0 0x11bca0 0 0x8c>;
> > > + reg-names = "freq-domain0", "freq-domain1";
> > > + #freq-domain-cells = <1>;
> > > + };
> > > + };
> > > +
> > > +
> > > +
> > > +
> > > --
> > > 1.7.9.5
>
On Fri, 2020-09-25 at 15:25 +0800, Hector Yuan wrote: > Hi, Rob sir: > > Yes, my patch follows > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt way to > define frequency domain. > Is it OK to you if I use the same way to do? > And if there exist any schema problem, please kindly let me know how to > fix it. > > My patch reference > Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml > to use the cpu node. > https://elixir.bootlin.com/linux/v5.9-rc6/source/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml > > Thanks a lot. > Hi, Rob sir: Sorry to bother you, may we know your comment for this. Thanks so much. > On Fri, 2020-09-25 at 11:45 +0530, Viresh Kumar wrote: > > On 25-09-20, 10:27, Hector Yuan wrote: > > > Hi, Viresh & Rob Sir: > > > > > > I will change frequency domain to below and define it in cpufreq_hw > > > schema rather than cpu node. > > > > > > mediatek,freq-domain-0 = <&cpu0>, <&cpu1>; > > > > I think it would be better to do it the standard way we have done it elsewhere. > > i.e. follow Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt, that > > is similar to what you did earlier. > > >
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..118a163 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan <hector.yuan@mediatek.com> + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: "mediatek,cpufreq-hw" + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + + reg-names: + items: + - const: "freq-domain0" + - const: "freq-domain1" + description: | + Frequency domain name. i.e. + "freq-domain0", "freq-domain1". + + "#freq-domain-cells": + const: 1 + description: | + Number of cells in a freqency domain specifier. + + mtk-freq-domain: + maxItems: 1 + description: | + Define this cpu belongs to which frequency domain. i.e. + cpu0-3 belong to frequency domain0, + cpu4-6 belong to frequency domain1. + +required: + - compatible + - reg + - reg-names + - "#freq-domain-cells" + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells = <2>; + #size-cells = <2>; + + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + reg-names = "freq-domain0", "freq-domain1"; + #freq-domain-cells = <1>; + }; + }; + + + +