| Message ID | 5e41140ddb1afe42699715cca59c44fa2fa29e60.1596028601.git.guillaume.tucker@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] ARM: exynos: clear L220_AUX_CTRL_NS_LOCKDOWN in default l2c_aux_val | expand |
On Wed, Jul 29, 2020 at 02:47:33PM +0100, Guillaume Tucker wrote: > Use the standard l2c2x0 device tree bindings to enable data and > instruction prefetch on exynos4210 and exynos4412 and clear the > respective bits in the default l2c_aux_val. No other Exynos platform > relying on this default register value appears to be using the l2x0 > cache. > > Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> > --- > arch/arm/boot/dts/exynos4210.dtsi | 2 ++ > arch/arm/boot/dts/exynos4412.dtsi | 2 ++ > arch/arm/mach-exynos/exynos.c | 4 ++-- I will need these split between DTS and mach changes. Best regards, Krzysztof
On 03/08/2020 14:13, Krzysztof Kozlowski wrote: > On Wed, Jul 29, 2020 at 02:47:33PM +0100, Guillaume Tucker wrote: >> Use the standard l2c2x0 device tree bindings to enable data and >> instruction prefetch on exynos4210 and exynos4412 and clear the >> respective bits in the default l2c_aux_val. No other Exynos platform >> relying on this default register value appears to be using the l2x0 >> cache. >> >> Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> >> --- >> arch/arm/boot/dts/exynos4210.dtsi | 2 ++ >> arch/arm/boot/dts/exynos4412.dtsi | 2 ++ >> arch/arm/mach-exynos/exynos.c | 4 ++-- > > I will need these split between DTS and mach changes. Of course, sorry. Fixed in v2. Thanks, Guillaume
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b4466232f0c1..7e0d253b26ef 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -102,6 +102,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <2 2 1>; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 48868947373e..37efa247bf4d 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -218,6 +218,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <3 2 1>; arm,double-linefill = <1>; diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index a96f3353a0c1..0e906cc3a48e 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -193,8 +193,8 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x38400000, - .l2c_aux_mask = 0xc60fffff, + .l2c_aux_val = 0x08400000, + .l2c_aux_mask = 0xf60fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init,
Use the standard l2c2x0 device tree bindings to enable data and instruction prefetch on exynos4210 and exynos4412 and clear the respective bits in the default l2c_aux_val. No other Exynos platform relying on this default register value appears to be using the l2x0 cache. Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> --- arch/arm/boot/dts/exynos4210.dtsi | 2 ++ arch/arm/boot/dts/exynos4412.dtsi | 2 ++ arch/arm/mach-exynos/exynos.c | 4 ++-- 3 files changed, 6 insertions(+), 2 deletions(-) -- 2.20.1