diff mbox series

[v2] pinctrl: qcom: sm8250: correct sdc2_clk and ngpios

Message ID 20200914001229.47290-1-dmitry.baryshkov@linaro.org
State Superseded
Headers show
Series [v2] pinctrl: qcom: sm8250: correct sdc2_clk and ngpios | expand

Commit Message

Dmitry Baryshkov Sept. 14, 2020, 12:12 a.m. UTC
Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has
180 GPIO pins).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

---
 drivers/pinctrl/qcom/pinctrl-sm8250.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.28.0

Comments

Bjorn Andersson Sept. 14, 2020, 12:23 a.m. UTC | #1
On Sun 13 Sep 19:12 CDT 2020, Dmitry Baryshkov wrote:

> Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has

> 180 GPIO pins).


The second half of the message is no longer relevant, and you only need
one of your s-o-b below.

Regards,
Bjorn

> 

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---

>  drivers/pinctrl/qcom/pinctrl-sm8250.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c

> index a660f1274b66..826df0d637ea 100644

> --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c

> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c

> @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = {

>  	[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),

>  	[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),

>  	[180] = UFS_RESET(ufs_reset, 0xb8000),

> -	[181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6),

> +	[181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),

>  	[182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),

>  	[183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),

>  };

> -- 

> 2.28.0

>
Dmitry Baryshkov Sept. 14, 2020, 9:19 a.m. UTC | #2
On Mon, 14 Sep 2020 at 03:23, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>

> On Sun 13 Sep 19:12 CDT 2020, Dmitry Baryshkov wrote:

>

> > Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has

> > 180 GPIO pins).

>

> The second half of the message is no longer relevant, and you only need

> one of your s-o-b below.


I should stop sending patches at 3 a.m.




-- 
With best wishes
Dmitry
diff mbox series

Patch

diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c
index a660f1274b66..826df0d637ea 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -1308,7 +1308,7 @@  static const struct msm_pingroup sm8250_groups[] = {
 	[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
 	[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
 	[180] = UFS_RESET(ufs_reset, 0xb8000),
-	[181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6),
+	[181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
 	[182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
 	[183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
 };