diff mbox series

[01/77] tests/tcg: Add microblaze to arches filter

Message ID	20200825205950.730499-2-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 01/77] tests/tcg: Add microblaze to arches filter Date: Tue, 25 Aug 2020 13:58:34 -0700 Message-Id: <20200825205950.730499-2-richard.henderson@linaro.org> In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com Precedence: list Cc: edgar.iglesias@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/microblaze improvements \| expand [00/77] target/microblaze improvements [01/77] tests/tcg: Add microblaze to arches filter [02/77] tests/tcg: Do not require FE_TOWARDZERO [03/77] tests/tcg: Do not require FE_* exception bits [04/77] target/microblaze: Tidy gdbstub [05/77] target/microblaze: Split out PC from env->sregs [06/77] target/microblaze: Split out MSR from env->sregs [07/77] target/microblaze: Split out EAR from env->sregs [08/77] target/microblaze: Split out ESR from env->sregs [09/77] target/microblaze: Split out FSR from env->sregs [10/77] target/microblaze: Split out BTR from env->sregs [11/77] target/microblaze: Split out EDR from env->sregs [12/77] target/microblaze: Split the cpu_SR array [13/77] target/microblaze: Fix width of PC and BTARGET [14/77] target/microblaze: Fix width of MSR [15/77] target/microblaze: Fix width of ESR [16/77] target/microblaze: Fix width of FSR [17/77] target/microblaze: Fix width of BTR [18/77] target/microblaze: Fix width of EDR [19/77] target/microblaze: Remove cpu_ear [20/77] target/microblaze: Tidy raising of exceptions [21/77] target/microblaze: Mark raise_exception as noreturn [22/77] target/microblaze: Remove helper_debug and env->debug [23/77] target/microblaze: Rename env_* tcg variables to cpu_* [24/77] target/microblaze: Tidy mb_tcg_init [25/77] target/microblaze: Split out MSR[C] to its own variable [26/77] target/microblaze: Use DISAS_NORETURN [27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb [28/77] target/microblaze: Convert to DisasContextBase [29/77] target/microblaze: Convert to translator_loop [30/77] target/microblaze: Remove SIM_COMPAT [31/77] target/microblaze: Remove DISAS_GNU [32/77] target/microblaze: Remove empty D macros [33/77] target/microblaze: Remove LOG_DIS [34/77] target/microblaze: Ensure imm constant is always available [35/77] target/microblaze: Add decodetree infrastructure [36/77] target/microblaze: Convert dec_add to decodetree [37/77] target/microblaze: Convert dec_sub to decodetree [38/77] target/microblaze: Implement cmp and cmpu inline [39/77] target/microblaze: Convert dec_pattern to decodetree [40/77] target/microblaze: Convert dec_and, dec_or, dec_xor to decodetree [41/77] target/microblaze: Convert dec_mul to decodetree [42/77] target/microblaze: Convert dec_div to decodetree [43/77] target/microblaze: Unwind properly when raising divide-by-zero [44/77] target/microblaze: Convert dec_bit to decodetree [45/77] target/microblaze: Convert dec_barrel to decodetree [46/77] target/microblaze: Convert dec_imm to decodetree [47/77] target/microblaze: Convert dec_fpu to decodetree [48/77] target/microblaze: Fix cpu unwind for fpu exceptions [49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG [50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE [51/77] target/microblaze: Cache mem_index in DisasContext [52/77] target/microblaze: Fix cpu unwind for stackprot [53/77] target/microblaze: Convert dec_load and dec_store to decodetree [54/77] target/microblaze: Assert no overlap in flags making up tb_flags [55/77] target/microblaze: Move bimm to BIMM_FLAG [56/77] target/microblaze: Store "current" iflags in insn_start [57/77] tcg: Add tcg_get_insn_start_param [58/77] target/microblaze: Use cc->do_unaligned_access [59/77] target/microblaze: Replace clear_imm with tb_flags_to_set [60/77] target/microblaze: Replace delayed_branch with tb_flags_to_set [61/77] target/microblaze: Tidy mb_cpu_dump_state [62/77] target/microblaze: Try to keep imm and delay slot together [63/77] target/microblaze: Convert brk and brki to decodetree [64/77] target/microblaze: Convert mbar to decodetree [65/77] target/microblaze: Reorganize branching [66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr [67/77] target/microblaze: Convert dec_br to decodetree [68/77] target/microblaze: Convert dec_bcc to decodetree [69/77] target/microblaze: Convert dec_rts to decodetree [70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte [71/77] target/microblaze: Convert msrclr, msrset to decodetree [72/77] target/microblaze: Convert dec_msr to decodetree [73/77] target/microblaze: Convert dec_stream to decodetree [74/77] target/microblaze: Remove last of old decoder [75/77] target/microblaze: Remove cpu_R[0] [76/77] target/microblaze: Add flags markup to some helpers [77/77] target/microblaze: Reduce linux-user address space to 32-bit

Commit Message

Richard Henderson Aug. 25, 2020, 8:58 p.m. UTC

Not attempting to use a single cross-compiler for both
big-endian and little-endian at this time.

Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tests/tcg/configure.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.25.1

Comments

Edgar E. Iglesias Aug. 26, 2020, 4:20 p.m. UTC | #1

On Tue, Aug 25, 2020 at 01:58:34PM -0700, Richard Henderson wrote:
> Not attempting to use a single cross-compiler for both

> big-endian and little-endian at this time.

> 

> Cc: Alex Bennée <alex.bennee@linaro.org>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> ---

>  tests/tcg/configure.sh | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh

> index 7d714f902a..598a50cd4f 100755

> --- a/tests/tcg/configure.sh

> +++ b/tests/tcg/configure.sh

> @@ -94,7 +94,7 @@ for target in $target_list; do

>      xtensa|xtensaeb)

>        arches=xtensa

>        ;;

> -    alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64)

> +    alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64)

>        arches=$target

>        ;;

>      *)

> -- 

> 2.25.1

>

diff mbox series

Patch

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 7d714f902a..598a50cd4f 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -94,7 +94,7 @@  for target in $target_list; do
     xtensa|xtensaeb)
       arches=xtensa
       ;;
-    alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64)
+    alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64)
       arches=$target
       ;;
     *)