| Message ID | 20200803205708.315829-1-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [for-5.1] docs/devel: Document decodetree no-overlap groups | expand |
On Mon, 3 Aug 2020 at 21:57, Richard Henderson <richard.henderson@linaro.org> wrote: > > When support for this feature went in, the update to the > documentation was forgotten. > > Fixes: 067e8b0f45d6 > Reported-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- > 1 file changed, 18 insertions(+), 11 deletions(-) > @@ -200,7 +207,7 @@ instruction:: > When the *cf* field is zero, the instruction has no side effects, > and may be specialized. When the *rt* field is zero, the output > is discarded and so the instruction has no effect. When the *rt2* > -field is zero, the operation is ``reg[rt] | 0`` and so encodes > +field is zero, the operation is ``reg[r1] | 0`` and so encodes > the canonical register copy operation. Technically a separate change, but a very small one... Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On Tue, 4 Aug 2020 at 10:38, Peter Maydell <peter.maydell@linaro.org> wrote: > > On Mon, 3 Aug 2020 at 21:57, Richard Henderson > <richard.henderson@linaro.org> wrote: > > > > When support for this feature went in, the update to the > > documentation was forgotten. > > > > Fixes: 067e8b0f45d6 > > Reported-by: Peter Maydell <peter.maydell@linaro.org> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > --- > > docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- > > 1 file changed, 18 insertions(+), 11 deletions(-) > > > @@ -200,7 +207,7 @@ instruction:: > > When the *cf* field is zero, the instruction has no side effects, > > and may be specialized. When the *rt* field is zero, the output > > is discarded and so the instruction has no effect. When the *rt2* > > -field is zero, the operation is ``reg[rt] | 0`` and so encodes > > +field is zero, the operation is ``reg[r1] | 0`` and so encodes > > the canonical register copy operation. > > Technically a separate change, but a very small one... > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> I'll take this via target-arm.next since I have something else to go into rc3 as well. -- PMM
diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst index ce7f52308f..74f66bf46e 100644 --- a/docs/devel/decodetree.rst +++ b/docs/devel/decodetree.rst @@ -173,18 +173,25 @@ Pattern Groups Syntax:: - group := '{' ( pat_def | group )+ '}' + group := overlap_group | no_overlap_group + overlap_group := '{' ( pat_def | group )+ '}' + no_overlap_group := '[' ( pat_def | group )+ ']' -A *group* begins with a lone open-brace, with all subsequent lines -indented two spaces, and ending with a lone close-brace. Groups -may be nested, increasing the required indentation of the lines -within the nested group to two spaces per nesting level. +A *group* begins with a lone open-brace or open-bracket, with all +subsequent lines indented two spaces, and ending with a lone +close-brace or close-bracket. Groups may be nested, increasing the +required indentation of the lines within the nested group to two +spaces per nesting level. -Unlike ungrouped patterns, grouped patterns are allowed to overlap. -Conflicts are resolved by selecting the patterns in order. If all -of the fixedbits for a pattern match, its translate function will -be called. If the translate function returns false, then subsequent -patterns within the group will be matched. +Patterns within overlap groups are allowed to overlap. Conflicts are +resolved by selecting the patterns in order. If all of the fixedbits +for a pattern match, its translate function will be called. If the +translate function returns false, then subsequent patterns within the +group will be matched. + +Patterns within no-overlap groups are not allowed to overlap, just +the same as ungrouped patterns. Thus no-overlap groups are intended +to be nested inside overlap groups. The following example from PA-RISC shows specialization of the *or* instruction:: @@ -200,7 +207,7 @@ instruction:: When the *cf* field is zero, the instruction has no side effects, and may be specialized. When the *rt* field is zero, the output is discarded and so the instruction has no effect. When the *rt2* -field is zero, the operation is ``reg[rt] | 0`` and so encodes +field is zero, the operation is ``reg[r1] | 0`` and so encodes the canonical register copy operation. The output from the generator might look like::
When support for this feature went in, the update to the documentation was forgotten. Fixes: 067e8b0f45d6 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) -- 2.25.1