| Message ID | 1595927918-19845-1-git-send-email-grzegorz.jaszczyk@linaro.org |
|---|---|
| Headers | show |
| Series | Add TI PRUSS Local Interrupt Controller IRQChip driver | expand |
On 2020-07-28 10:18, Grzegorz Jaszczyk wrote: > From: Suman Anna <s-anna@ti.com> > > The PRUSS INTC has a fixed number of output interrupt lines that are > connected to a number of processors or other PRUSS instances or other > devices (like DMA) on the SoC. The output interrupt lines 2 through 9 > are usually connected to the main Arm host processor and are referred > to as host interrupts 0 through 7 from ARM/MPU perspective. > > All of these 8 host interrupts are not always exclusively connected > to the Arm interrupt controller. Some SoCs have some interrupt lines > not connected to the Arm interrupt controller at all, while a few > others > have the interrupt lines connected to multiple processors in which they > need to be partitioned as per SoC integration needs. For example, > AM437x > and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt > 5 > connected to the other PRUSS, while AM335x has host interrupt 0 shared > between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU > and > a DMA controller. > > Add logic to the PRUSS INTC driver to ignore both these shared and > invalid interrupts. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > --- > v3->v4: > - Due to changes in DT bindings which converts irqs-reserved > property from uint8-array to bitmask requested by Rob introduce > relevant changes in the driver. > - Merge the irqs-reserved and irqs-shared to one property since they > can be handled by one logic (relevant change was introduced to DT > binding). This isn't what I asked for in my initial review. I repeatedly asked for the *handling* to be common, not for the properties to be merged. I don't mind either way, but I understood there were two properties for a good reason. Has this reason gone? Anyway, I'll come back to it once I start reviewing the series again. M. -- Jazz is not dead. It just smells funny...
On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > From: Suman Anna <s-anna@ti.com> > > The Programmable Real-Time Unit and Industrial Communication Subsystem > (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that > can handle various system input events and post interrupts back to the > device-level initiators. The INTC can support upto 64 input events on nit: "up to" is two separate words > most SoCs with individual control configuration and h/w prioritization. > These events are mapped onto 10 output interrupt lines through two levels > of many-to-one mapping support. Different interrupt lines are routed to > the individual PRU cores or to the host CPU or to other PRUSS instances. > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > a higher number of host interrupts (20 vs 10) and can handle an increased > number of input events (160 vs 64) from various SoC interrupt sources. > > Add the bindings document for these interrupt controllers on all the > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > and J721E SoCs. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Andrew F. Davis <afd@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > --- > v3->v4: > - Drop allOf references to interrupt-controller.yaml and > interrupts.yaml. > - Drop items descriptions and use only maxItems: 1 as suggested by Rob. > - Convert irqs-reserved property from uint8-array to bitmask. > - Minor descriptions updates. > - Change interrupt-cells to 3 in order to provide 2-level mapping > description for interrupts routed to the main CPU (as Marc requested). > - Merge the irqs-reserved and irqs-shared to one property since they > can be handled by one logic. > - Drop reviewed-by due to introduced changes. > - Add another example illustrating irqs-reserved property usage. > v2->v3: > - Convert dt-binding to YAML > v1->v2: > - https://patchwork.kernel.org/patch/11069767/ > --- > .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++++++++++++++++++ > 1 file changed, 157 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > new file mode 100644 > index 0000000..7336b11 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > @@ -0,0 +1,157 @@ > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI PRU-ICSS Local Interrupt Controller > + > +maintainers: > + - Suman Anna <s-anna@ti.com> > + > +description: | > + Each PRU-ICSS has a single interrupt controller instance that is common > + to all the PRU cores. Most interrupt controllers can route 64 input events > + which are then mapped to 10 possible output interrupts through two levels > + of mapping. The input events can be triggered by either the PRUs and/or > + various other PRUSS internal and external peripherals. The first 2 output > + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the > + remaining 8 (2 through 9) connected to external interrupt controllers > + including the MPU and/or other PRUSS instances, DSPs or devices. > + > + The property "ti,irqs-reserved" is used for denoting the connection > + differences on the output interrupts 2 through 9. If this property is not > + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 > + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt > + controller. > + > + The K3 family of SoCs can handle 160 input events that can be mapped to 20 > + different possible output interrupts. The additional output interrupts (10 > + through 19) are connected to new sub-modules within the ICSSG instances. > + > + This interrupt-controller node should be defined as a child node of the > + corresponding PRUSS node. The node should be named "interrupt-controller". > + > +properties: > + compatible: > + enum: > + - ti,pruss-intc > + - ti,icssg-intc > + description: | > + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, > + AM335x family of SoCs, > + AM437x family of SoCs, > + AM57xx family of SoCs > + 66AK2G family of SoCs > + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + maxItems: 8 > + description: | > + All the interrupts generated towards the main host processor in the SoC. > + A shared interrupt can be skipped if the desired destination and usage is > + by a different processor/device. This sounds like using device tree for configuration. Also, isn't this what the ti,irqs-reserved property is for? > + > + interrupt-names: > + minItems: 1 > + maxItems: 8 > + items: > + pattern: host_intr[0-7] > + description: | > + Should use one of the above names for each valid host event interrupt > + connected to Arm interrupt controller, the name should match the > + corresponding host event interrupt number. > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 3 > + description: | > + Client users shall use the PRU System event number (the interrupt source > + that the client is interested in), PRU channel and PRU host_intr (target) > + as the value of the interrupts property in their node. The system events > + can be mapped to some output host interrupts through 2 levels of > + many-to-one mapping i.e. events to channel mapping and channels to host > + interrupts so through this property entire mapping is provided. It is not clear what the meaning of each cell is. Looking at later patches, it looks like the first cell is the PRU system event number, the second cell is the channel and the third cell is the host event number. > + > + ti,irqs-reserved: > + $ref: /schemas/types.yaml#definitions/uint8 Is 8 bits enough for any possible future devices? It is written above that there are already up to 20 host events on some devices even if only 8 are connected to the MCU. > + description: | > + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC > + output interrupts 2 through 9) that are not connected to the Arm interrupt > + controller or are shared and used by other devices or processors in the > + SoC. Define this property when any of 8 interrupts should not be handled > + by Arm interrupt controller. > + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt > + connected to MPU > + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and > + "host_intr7" interrupts connected to MPU, and other ICSSG > + instances. > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - interrupt-controller > + - "#interrupt-cells" > + > +additionalProperties: false > + > +examples: > + - | > + /* AM33xx PRU-ICSS */ > + pruss: pruss@0 { > + compatible = "ti,am3356-pruss"; > + reg = <0x0 0x80000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pruss_intc: interrupt-controller@20000 { > + compatible = "ti,pruss-intc"; > + reg = <0x20000 0x2000>; > + interrupts = <20 21 22 23 24 25 26 27>; > + interrupt-names = "host_intr0", "host_intr1", > + "host_intr2", "host_intr3", > + "host_intr4", "host_intr5", > + "host_intr6", "host_intr7"; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + }; > + > + - | > + > + /* AM4376 PRU-ICSS */ > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + pruss@0 { > + compatible = "ti,am4376-pruss"; > + reg = <0x0 0x40000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + interrupt-controller@20000 { > + compatible = "ti,pruss-intc"; > + reg = <0x20000 0x2000>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "host_intr0", "host_intr1", > + "host_intr2", "host_intr3", > + "host_intr4", > + "host_intr6", "host_intr7"; > + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ Is 0b00100000 valid syntax in device tree (instead of 0x20 + comment)? > + }; > + }; >
On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > The Programmable Real-Time Unit Subsystem (PRUSS) contains a local > interrupt controller (INTC) that can handle various system input events > and post interrupts back to the device-level initiators. The INTC can > support upto 64 input events with individual control configuration and > hardware prioritization. These events are mapped onto 10 output interrupt > lines through two levels of many-to-one mapping support. Different > interrupt lines are routed to the individual PRU cores or to the host > CPU, or to other devices on the SoC. Some of these events are sourced > from peripherals or other sub-modules within that PRUSS, while a few > others are sourced from SoC-level peripherals/devices. > > The PRUSS INTC platform driver manages this PRUSS interrupt controller > and implements an irqchip driver to provide a Linux standard way for > the PRU client users to enable/disable/ack/re-trigger a PRUSS system > event. The system events to interrupt channels and output interrupts > relies on the mapping configuration provided either through the PRU > firmware blob (for interrupts routed to PRU cores) or via the PRU > application's device tree node (for interrupt routed to the main CPU). > In the first case the mappings will be programmed on PRU remoteproc > driver demand (via irq_create_fwspec_mapping) during the boot of a PRU > core and cleaned up after the PRU core is stopped. > > Reference counting is used to allow multiple system events to share a > single channel and to allow multiple channels to share a single host > event. > > The PRUSS INTC module is reference counted during the interrupt > setup phase through the irqchip's irq_request_resources() and > irq_release_resources() ops. This restricts the module from being > removed as long as there are active interrupt users. > > The driver currently supports and can be built for OMAP architecture > based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based > 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. > All of these SoCs support 64 system events, 10 interrupt channels and > 10 output interrupt lines per PRUSS INTC with a few SoC integration > differences. > > NOTE: > Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that > enables multiple external events to be routed to a specific number > of input interrupt events. Any non-default external interrupt event > directed towards PRUSS needs this crossbar to be setup properly. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Andrew F. Davis <afd@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > --- It looks like this patch also includes code that I wrote [1] so: Signed-off-by: David Lechner <david@lechnology.com> [1]: https://lore.kernel.org/lkml/124b03b8-f8e7-682b-8767-13a739329da2@lechnology.com/ > diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c > new file mode 100644 > index 0000000..45b966a > --- /dev/null > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -0,0 +1,591 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * PRU-ICSS INTC IRQChip driver for various TI SoCs > + * > + * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/ > + * Andrew F. Davis <afd@ti.com> > + * Suman Anna <s-anna@ti.com> Please add: + * Copyright (C) 2019 David Lechner <david@lechnology.com> > + */ > + > +#include <linux/irq.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/irqdomain.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > + > +/* > + * Number of host interrupts reaching the main MPU sub-system. Note that this > + * is not the same as the total number of host interrupts supported by the PRUSS > + * INTC instance > + */ > +#define MAX_NUM_HOST_IRQS 8 > + > +/* minimum starting host interrupt number for MPU */ > +#define MIN_PRU_HOST_INT 2 nit: "First" might be a better word choice than "minimum" > + > +/* PRU_ICSS_INTC registers */ > +#define PRU_INTC_REVID 0x0000 > +#define PRU_INTC_CR 0x0004 > +#define PRU_INTC_GER 0x0010 > +#define PRU_INTC_GNLR 0x001c > +#define PRU_INTC_SISR 0x0020 > +#define PRU_INTC_SICR 0x0024 > +#define PRU_INTC_EISR 0x0028 > +#define PRU_INTC_EICR 0x002c > +#define PRU_INTC_HIEISR 0x0034 > +#define PRU_INTC_HIDISR 0x0038 > +#define PRU_INTC_GPIR 0x0080 > +#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) > +#define PRU_INTC_SECR(x) (0x0280 + (x) * 4) > +#define PRU_INTC_ESR(x) (0x0300 + (x) * 4) > +#define PRU_INTC_ECR(x) (0x0380 + (x) * 4) > +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) > +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) > +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) > +#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4) > +#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4) > +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) > +#define PRU_INTC_HIER 0x1500 > + > +/* CMR register bit-field macros */ > +#define CMR_EVT_MAP_MASK 0xf > +#define CMR_EVT_MAP_BITS 8 > +#define CMR_EVT_PER_REG 4 > + > +/* HMR register bit-field macros */ > +#define HMR_CH_MAP_MASK 0xf > +#define HMR_CH_MAP_BITS 8 > +#define HMR_CH_PER_REG 4 > + > +/* HIPIR register bit-fields */ > +#define INTC_HIPIR_NONE_HINT 0x80000000 > + > +#define MAX_PRU_SYS_EVENTS 160 > +#define MAX_PRU_CHANNELS 20 > + > +/** > + * struct pruss_intc_map_record - keeps track of actual mapping state > + * @value: The currently mapped value (channel or host) > + * @ref_count: Keeps track of number of current users of this resource > + */ > +struct pruss_intc_map_record { > + u8 value; > + u8 ref_count; > +}; > + > +/** > + * struct pruss_intc_match_data - match data to handle SoC variations > + * @num_system_events: number of input system events handled by the PRUSS INTC > + * @num_host_intrs: number of host interrupts supported by the PRUSS INTC Do we also need the number of channels here? Or should this say "host event" instead of "host interrupt"? According to the proposed device tree spec, "host_intr" is the MCU interrupt event (0-7) which cooresponds to PRU host events 2-9. I suppose it is safe to assume that the number of channels is always equal to the number of host events. Maybe better to just say num_channels here instead of num_host_intrs here anyway even if it is used for both just to avoid potential confusion. > + */ > +struct pruss_intc_match_data { > + u8 num_system_events; > + u8 num_host_intrs; > +}; > + > +/** > + * struct pruss_intc - PRUSS interrupt controller structure > + * @event_channel: current state of system event to channel mappings > + * @channel_host: current state of channel to host mappings > + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts > + * @base: base virtual address of INTC register space > + * @domain: irq domain for this interrupt controller > + * @soc_config: cached PRUSS INTC IP configuration data > + * @dev: PRUSS INTC device pointer > + * @lock: mutex to serialize access to INTC It looks like this lock is just used to protect mapping and not all access to INTC, so maybe this description is not right? > + */ > +struct pruss_intc { > + struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS]; > + struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS]; > + unsigned int irqs[MAX_NUM_HOST_IRQS]; > + void __iomem *base; > + struct irq_domain *domain; > + const struct pruss_intc_match_data *soc_config; > + struct device *dev; > + struct mutex lock; /* PRUSS INTC lock */ > +}; > + > +/** > + * struct pruss_host_irq_data - PRUSS host irq data structure > + * @intc: PRUSS interrupt controller pointer > + * @host_irq: host irq number > + */ > +struct pruss_host_irq_data { > + struct pruss_intc *intc; > + u8 host_irq; > +}; > + > +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) > +{ > + return readl_relaxed(intc->base + reg); > +} > + > +static inline void pruss_intc_write_reg(struct pruss_intc *intc, > + unsigned int reg, u32 val) > +{ > + writel_relaxed(val, intc->base + reg); > +} > + > +static void pruss_intc_update_cmr(struct pruss_intc *intc, int evt, s8 ch) > +{ > + u32 idx, offset, val; > + > + idx = evt / CMR_EVT_PER_REG; > + offset = (evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS; > + > + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); > + val &= ~(CMR_EVT_MAP_MASK << offset); > + val |= ch << offset; > + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); > + > + dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch, > + idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); > +} > + > +static void pruss_intc_update_hmr(struct pruss_intc *intc, int ch, s8 host) > +{ > + u32 idx, offset, val; > + > + idx = ch / HMR_CH_PER_REG; > + offset = (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS; > + > + val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)); > + val &= ~(HMR_CH_MAP_MASK << offset); > + val |= host << offset; > + pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val); > + > + dev_dbg(intc->dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx, > + pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); > +} > + > +/** > + * pruss_intc_map() - configure the PRUSS INTC > + * @intc: PRUSS interrupt controller pointer > + * @hwirq: the system event number > + * > + * Configures the PRUSS INTC with the provided configuration from the one parsed > + * in the xlate function. > + */ > +static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) > +{ > + struct device *dev = intc->dev; > + u8 ch, host, reg_idx; > + u32 val; > + > + mutex_lock(&intc->lock); > + > + intc->event_channel[hwirq].ref_count++; > + > + ch = intc->event_channel[hwirq].value; > + host = intc->channel_host[ch].value; > + > + pruss_intc_update_cmr(intc, hwirq, ch); > + > + reg_idx = hwirq / 32; > + val = BIT(hwirq % 32); > + > + /* clear and enable system event */ > + pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val); > + pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); > + > + if (++intc->channel_host[ch].ref_count == 1) { > + pruss_intc_update_hmr(intc, ch, host); > + > + /* enable host interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host); > + } > + > + dev_dbg(dev, "mapped system_event = %lu channel = %d host = %d", > + hwirq, ch, host); > + > + /* global interrupt enable */ > + pruss_intc_write_reg(intc, PRU_INTC_GER, 1); > + > + mutex_unlock(&intc->lock); > +} > + > +/** > + * pruss_intc_unmap() - unconfigure the PRUSS INTC > + * @intc: PRUSS interrupt controller pointer > + * @hwirq: the system event number > + * > + * Undo whatever was done in pruss_intc_map() for a PRU core. > + * Mappings are reference counted, so resources are only disabled when there > + * are no longer any users. > + */ > +static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) > +{ > + u8 ch, host, reg_idx; > + u32 val; > + > + mutex_lock(&intc->lock); > + > + ch = intc->event_channel[hwirq].value; > + host = intc->channel_host[ch].value; > + > + if (--intc->channel_host[ch].ref_count == 0) { > + /* disable host interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host); > + > + /* clear the map using reset value 0 */ > + pruss_intc_update_hmr(intc, ch, 0); > + } > + > + intc->event_channel[hwirq].ref_count--; > + reg_idx = hwirq / 32; > + val = BIT(hwirq % 32); > + > + /* disable system events */ > + pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val); > + /* clear any pending status */ > + pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); > + > + /* clear the map using reset value 0 */ > + pruss_intc_update_cmr(intc, hwirq, 0); > + > + dev_dbg(intc->dev, "unmapped system_event = %lu channel = %d host = %d\n", > + hwirq, ch, host); > + > + mutex_unlock(&intc->lock); > +} > + > +static void pruss_intc_init(struct pruss_intc *intc) > +{ > + const struct pruss_intc_match_data *soc_config = intc->soc_config; > + int i; > + int num_chnl_map_regs = DIV_ROUND_UP(soc_config->num_system_events, > + CMR_EVT_PER_REG); > + int num_host_intr_regs = DIV_ROUND_UP(soc_config->num_host_intrs, > + HMR_CH_PER_REG); > + int num_event_type_regs = > + DIV_ROUND_UP(soc_config->num_system_events, 32); > + > + /* > + * configure polarity (SIPR register) to active high and > + * type (SITR register) to level interrupt for all system events > + */ > + for (i = 0; i < num_event_type_regs; i++) { > + pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff); > + pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0); > + } > + > + /* clear all interrupt channel map registers, 4 events per register */ > + for (i = 0; i < num_chnl_map_regs; i++) > + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); > + > + /* clear all host interrupt map registers, 4 channels per register */ > + for (i = 0; i < num_host_intr_regs; i++) > + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); > +} > + > +static void pruss_intc_irq_ack(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); > +} > + > +static void pruss_intc_irq_mask(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq); > +} > + > +static void pruss_intc_irq_unmask(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq); > +} > + > +static int pruss_intc_irq_reqres(struct irq_data *data) > +{ > + if (!try_module_get(THIS_MODULE)) > + return -ENODEV; > + > + return 0; > +} > + > +static void pruss_intc_irq_relres(struct irq_data *data) > +{ > + module_put(THIS_MODULE); > +} > + > +static struct irq_chip pruss_irqchip = { > + .name = "pruss-intc", > + .irq_ack = pruss_intc_irq_ack, > + .irq_mask = pruss_intc_irq_mask, > + .irq_unmask = pruss_intc_irq_unmask, > + .irq_request_resources = pruss_intc_irq_reqres, > + .irq_release_resources = pruss_intc_irq_relres, > +}; > + > +static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event, > + int channel, int host) > +{ > + struct device *dev = intc->dev; > + int ret = 0; > + > + mutex_lock(&intc->lock); > + > + /* check if sysevent already assigned */ > + if (intc->event_channel[event].ref_count > 0 && > + intc->event_channel[event].value != channel) { > + dev_err(dev, "event %d (req. ch %d) already assigned to channel %d\n", > + event, channel, intc->event_channel[event].value); > + ret = -EBUSY; > + goto unlock; > + } > + > + /* check if channel already assigned */ > + if (intc->channel_host[channel].ref_count > 0 && > + intc->channel_host[channel].value != host) { > + dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n", > + channel, host, intc->channel_host[channel].value); > + ret = -EBUSY; > + goto unlock; > + } > + > + intc->event_channel[event].value = channel; > + intc->channel_host[channel].value = host; > + > +unlock: > + mutex_unlock(&intc->lock); > + return ret; > +} > + > +static int > +pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node, > + const u32 *intspec, unsigned int intsize, > + unsigned long *out_hwirq, unsigned int *out_type) > +{ > + struct pruss_intc *intc = d->host_data; > + struct device *dev = intc->dev; > + int ret, sys_event, channel, host; > + > + if (intsize < 3) > + return -EINVAL; > + > + sys_event = intspec[0]; > + if (sys_event < 0 || sys_event >= intc->soc_config->num_system_events) { > + dev_err(dev, "%d is not valid event number\n", sys_event); > + return -EINVAL; > + } > + > + channel = intspec[1]; > + if (channel < 0 || channel >= intc->soc_config->num_host_intrs) { > + dev_err(dev, "%d is not valid channel number", channel); > + return -EINVAL; > + } > + > + host = intspec[2]; > + if (host < 0 || host >= intc->soc_config->num_host_intrs) { > + dev_err(dev, "%d is not valid host irq number\n", host); > + return -EINVAL; > + } > + > + /* check if requested sys_event was already mapped, if so validate it */ > + ret = pruss_intc_validate_mapping(intc, sys_event, channel, host); > + if (ret) > + return ret; > + > + *out_hwirq = sys_event; > + *out_type = IRQ_TYPE_NONE; > + > + return 0; > +} > + > +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, > + irq_hw_number_t hw) > +{ > + struct pruss_intc *intc = d->host_data; > + > + pruss_intc_map(intc, hw); > + > + irq_set_chip_data(virq, intc); > + irq_set_chip_and_handler(virq, &pruss_irqchip, handle_level_irq); > + > + return 0; > +} > + > +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) > +{ > + struct pruss_intc *intc = d->host_data; > + unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); > + > + irq_set_chip_and_handler(virq, NULL, NULL); > + irq_set_chip_data(virq, NULL); > + pruss_intc_unmap(intc, hwirq); > +} > + > +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { > + .xlate = pruss_intc_irq_domain_xlate, > + .map = pruss_intc_irq_domain_map, > + .unmap = pruss_intc_irq_domain_unmap, > +}; > + > +static void pruss_intc_irq_handler(struct irq_desc *desc) > +{ > + unsigned int irq = irq_desc_get_irq(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + struct pruss_host_irq_data *host_irq_data = irq_get_handler_data(irq); > + struct pruss_intc *intc = host_irq_data->intc; > + u32 hipir; > + unsigned int virq; > + int hwirq; > + u8 host_irq = host_irq_data->host_irq + MIN_PRU_HOST_INT; > + > + chained_irq_enter(chip, desc); > + > + while (true) { > + /* get highest priority pending PRUSS system event */ > + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(host_irq)); > + if (hipir & INTC_HIPIR_NONE_HINT) > + break; > + > + hwirq = hipir & GENMASK(9, 0); > + virq = irq_find_mapping(intc->domain, hwirq); > + > + /* > + * NOTE: manually ACK any system events that do not have a > + * handler mapped yet > + */ > + if (WARN_ON_ONCE(!virq)) > + pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq); > + else > + generic_handle_irq(virq); > + } > + > + chained_irq_exit(chip, desc); > +} > + > +static int pruss_intc_probe(struct platform_device *pdev) > +{ > + static const char * const irq_names[MAX_NUM_HOST_IRQS] = { > + "host_intr0", "host_intr1", "host_intr2", "host_intr3", > + "host_intr4", "host_intr5", "host_intr6", "host_intr7", }; > + const struct pruss_intc_match_data *data; > + struct device *dev = &pdev->dev; > + struct pruss_intc *intc; > + struct pruss_host_irq_data *host_data[MAX_NUM_HOST_IRQS] = { NULL }; > + int i, irq, ret; > + u8 max_system_events; > + > + data = of_device_get_match_data(dev); > + if (!data) > + return -ENODEV; > + > + max_system_events = data->num_system_events; > + > + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); > + if (!intc) > + return -ENOMEM; > + > + intc->soc_config = data; > + intc->dev = dev; > + platform_set_drvdata(pdev, intc); > + > + intc->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(intc->base)) { > + dev_err(dev, "failed to parse and map intc memory resource\n"); devm_platform_ioremap_resource() already prints an error message on error, so dev_err() here is redundant. > + return PTR_ERR(intc->base); > + } > + > + pruss_intc_init(intc); > + > + mutex_init(&intc->lock); > + > + intc->domain = irq_domain_add_linear(dev->of_node, max_system_events, > + &pruss_intc_irq_domain_ops, intc); > + if (!intc->domain) > + return -ENOMEM; > + > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > + irq = platform_get_irq_byname(pdev, irq_names[i]); > + if (irq <= 0) { > + dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", > + irq_names[i], irq); platform_get_irq_byname() already prints a message on error. If irq == 0 then ret is being set to 0 but we jump to fail_irq. This doesn't seem right. > + ret = irq; > + goto fail_irq; > + } > + > + intc->irqs[i] = irq; > + > + host_data[i] = devm_kzalloc(dev, sizeof(*host_data[0]), > + GFP_KERNEL); > + if (!host_data[i]) { > + ret = -ENOMEM; > + goto fail_irq; > + } > + > + host_data[i]->intc = intc; > + host_data[i]->host_irq = i; > + > + irq_set_handler_data(irq, host_data[i]); > + irq_set_chained_handler(irq, pruss_intc_irq_handler); > + } > + > + return 0; > + > +fail_irq: > + while (--i >= 0) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); > + > + irq_domain_remove(intc->domain); > + > + return ret; > +} > + > +static int pruss_intc_remove(struct platform_device *pdev) > +{ > + struct pruss_intc *intc = platform_get_drvdata(pdev); > + u8 max_system_events = intc->soc_config->num_system_events; > + unsigned int hwirq; > + int i; > + > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); > + > + for (hwirq = 0; hwirq < max_system_events; hwirq++) > + irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); > + > + irq_domain_remove(intc->domain); > + > + return 0; > +} > + > +static const struct pruss_intc_match_data pruss_intc_data = { > + .num_system_events = 64, > + .num_host_intrs = 10, > +}; > + > +static const struct of_device_id pruss_intc_of_match[] = { > + { > + .compatible = "ti,pruss-intc", > + .data = &pruss_intc_data, > + }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); > + > +static struct platform_driver pruss_intc_driver = { > + .driver = { > + .name = "pruss-intc", > + .of_match_table = pruss_intc_of_match, > + .suppress_bind_attrs = true, Just curious - why do we need to supress bind? > + }, > + .probe = pruss_intc_probe, > + .remove = pruss_intc_remove, > +}; > +module_platform_driver(pruss_intc_driver); > + > +MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); > +MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); > +MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>"); > +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver"); > +MODULE_LICENSE("GPL v2"); >
On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > From: Suman Anna <s-anna@ti.com> > > The PRUSS INTC has a fixed number of output interrupt lines that are > connected to a number of processors or other PRUSS instances or other > devices (like DMA) on the SoC. The output interrupt lines 2 through 9 > are usually connected to the main Arm host processor and are referred > to as host interrupts 0 through 7 from ARM/MPU perspective. > > All of these 8 host interrupts are not always exclusively connected > to the Arm interrupt controller. Some SoCs have some interrupt lines > not connected to the Arm interrupt controller at all, while a few others > have the interrupt lines connected to multiple processors in which they > need to be partitioned as per SoC integration needs. For example, AM437x > and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5 > connected to the other PRUSS, while AM335x has host interrupt 0 shared > between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and > a DMA controller. > > Add logic to the PRUSS INTC driver to ignore both these shared and > invalid interrupts. If a person wanted to use DMA with a PRU what will handle the mapping of a PRU event to host interrupt 6 or 7 if they are being ignored here? > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > --- > v3->v4: > - Due to changes in DT bindings which converts irqs-reserved > property from uint8-array to bitmask requested by Rob introduce > relevant changes in the driver. > - Merge the irqs-reserved and irqs-shared to one property since they > can be handled by one logic (relevant change was introduced to DT > binding). > - Update commit message. > v2->v3: > - Extra checks for (intc->irqs[i]) in error/remove path was moved from > "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS > interrupts" to this patch > v1->v2: > - https://patchwork.kernel.org/patch/11069757/ > --- > drivers/irqchip/irq-pruss-intc.c | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c > index 45b966a..cf9a59b 100644 > --- a/drivers/irqchip/irq-pruss-intc.c > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -474,7 +474,7 @@ static int pruss_intc_probe(struct platform_device *pdev) > struct pruss_intc *intc; > struct pruss_host_irq_data *host_data[MAX_NUM_HOST_IRQS] = { NULL }; > int i, irq, ret; > - u8 max_system_events; > + u8 max_system_events, invalid_intr = 0; > > data = of_device_get_match_data(dev); > if (!data) > @@ -496,6 +496,16 @@ static int pruss_intc_probe(struct platform_device *pdev) > return PTR_ERR(intc->base); > } > > + ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved", > + &invalid_intr); Why not make the variable name match the property name? > + > + /* > + * The irqs-reserved is used only for some SoC's therefore not having > + * this property is still valid > + */ > + if (ret < 0 && ret != -EINVAL) > + return ret; > + > pruss_intc_init(intc); > > mutex_init(&intc->lock); > @@ -506,6 +516,9 @@ static int pruss_intc_probe(struct platform_device *pdev) > return -ENOMEM; > > for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > + if (invalid_intr & BIT(i)) > + continue; > + > irq = platform_get_irq_byname(pdev, irq_names[i]); > if (irq <= 0) { > dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", > @@ -533,8 +546,11 @@ static int pruss_intc_probe(struct platform_device *pdev) > return 0; > > fail_irq: > - while (--i >= 0) > - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); > + while (--i >= 0) { > + if (intc->irqs[i]) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, > + NULL); > + } > > irq_domain_remove(intc->domain); > > @@ -548,8 +564,11 @@ static int pruss_intc_remove(struct platform_device *pdev) > unsigned int hwirq; > int i; > > - for (i = 0; i < MAX_NUM_HOST_IRQS; i++) > - irq_set_chained_handler_and_data(intc->irqs[i], NULL, NULL); > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > + if (intc->irqs[i]) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, > + NULL); > + } > > for (hwirq = 0; hwirq < max_system_events; hwirq++) > irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); >
On Wed, 29 Jul 2020 at 19:34, David Lechner <david@lechnology.com> wrote: > > On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > > From: Suman Anna <s-anna@ti.com> > > > > The Programmable Real-Time Unit and Industrial Communication Subsystem > > (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that > > can handle various system input events and post interrupts back to the > > device-level initiators. The INTC can support upto 64 input events on > > nit: "up to" is two separate words Ok. > > > most SoCs with individual control configuration and h/w prioritization. > > These events are mapped onto 10 output interrupt lines through two levels > > of many-to-one mapping support. Different interrupt lines are routed to > > the individual PRU cores or to the host CPU or to other PRUSS instances. > > > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > > a higher number of host interrupts (20 vs 10) and can handle an increased > > number of input events (160 vs 64) from various SoC interrupt sources. > > > > Add the bindings document for these interrupt controllers on all the > > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > > and J721E SoCs. > > > > Signed-off-by: Suman Anna <s-anna@ti.com> > > Signed-off-by: Andrew F. Davis <afd@ti.com> > > Signed-off-by: Roger Quadros <rogerq@ti.com> > > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > > --- > > v3->v4: > > - Drop allOf references to interrupt-controller.yaml and > > interrupts.yaml. > > - Drop items descriptions and use only maxItems: 1 as suggested by Rob. > > - Convert irqs-reserved property from uint8-array to bitmask. > > - Minor descriptions updates. > > - Change interrupt-cells to 3 in order to provide 2-level mapping > > description for interrupts routed to the main CPU (as Marc requested). > > - Merge the irqs-reserved and irqs-shared to one property since they > > can be handled by one logic. > > - Drop reviewed-by due to introduced changes. > > - Add another example illustrating irqs-reserved property usage. > > v2->v3: > > - Convert dt-binding to YAML > > v1->v2: > > - https://patchwork.kernel.org/patch/11069767/ > > --- > > .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++++++++++++++++++ > > 1 file changed, 157 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > new file mode 100644 > > index 0000000..7336b11 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > @@ -0,0 +1,157 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: TI PRU-ICSS Local Interrupt Controller > > + > > +maintainers: > > + - Suman Anna <s-anna@ti.com> > > + > > +description: | > > + Each PRU-ICSS has a single interrupt controller instance that is common > > + to all the PRU cores. Most interrupt controllers can route 64 input events > > + which are then mapped to 10 possible output interrupts through two levels > > + of mapping. The input events can be triggered by either the PRUs and/or > > + various other PRUSS internal and external peripherals. The first 2 output > > + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the > > + remaining 8 (2 through 9) connected to external interrupt controllers > > + including the MPU and/or other PRUSS instances, DSPs or devices. > > + > > + The property "ti,irqs-reserved" is used for denoting the connection > > + differences on the output interrupts 2 through 9. If this property is not > > + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 > > + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt > > + controller. > > + > > + The K3 family of SoCs can handle 160 input events that can be mapped to 20 > > + different possible output interrupts. The additional output interrupts (10 > > + through 19) are connected to new sub-modules within the ICSSG instances. > > + > > + This interrupt-controller node should be defined as a child node of the > > + corresponding PRUSS node. The node should be named "interrupt-controller". > > + > > +properties: > > + compatible: > > + enum: > > + - ti,pruss-intc > > + - ti,icssg-intc > > + description: | > > + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, > > + AM335x family of SoCs, > > + AM437x family of SoCs, > > + AM57xx family of SoCs > > + 66AK2G family of SoCs > > + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 8 > > + description: | > > + All the interrupts generated towards the main host processor in the SoC. > > + A shared interrupt can be skipped if the desired destination and usage is > > + by a different processor/device. > > This sounds like using device tree for configuration. Also, isn't this what the > ti,irqs-reserved property is for? Yes this is what ti,irqs-reserved is also used for. The intention was to keep both in sync, so it would be less confusing: if some interrupts are on irqs-reserved list, they shouldn't be present here. In terms of shared interrupt usage I will not call it configuration via device-tree, rather design description (for single device tree description given shared interrupt is used or as MCPU one or as different processor/device one). > > > + > > + interrupt-names: > > + minItems: 1 > > + maxItems: 8 > > + items: > > + pattern: host_intr[0-7] > > + description: | > > + Should use one of the above names for each valid host event interrupt > > + connected to Arm interrupt controller, the name should match the > > + corresponding host event interrupt number. > > + > > + interrupt-controller: true > > + > > + "#interrupt-cells": > > + const: 3 > > + description: | > > + Client users shall use the PRU System event number (the interrupt source > > + that the client is interested in), PRU channel and PRU host_intr (target) > > + as the value of the interrupts property in their node. The system events > > + can be mapped to some output host interrupts through 2 levels of > > + many-to-one mapping i.e. events to channel mapping and channels to host > > + interrupts so through this property entire mapping is provided. > > It is not clear what the meaning of each cell is. Looking at later patches, it > looks like the first cell is the PRU system event number, the second cell is the > channel and the third cell is the host event number. Ok, how about updating above description like this: Client users shall use the PRU System event number (the interrupt source that the client is interested in) [cell 1], PRU channel [cell 2] and PRU host_intr (target) [cell 3] as the value of the interrupts property in their node. The system events can be mapped to some output host interrupts through 2 levels of many-to-one mapping i.e. events to channel mapping and channels to host interrupts so through this property entire mapping is provided. > > > + > > + ti,irqs-reserved: > > + $ref: /schemas/types.yaml#definitions/uint8 > > Is 8 bits enough for any possible future devices? It is written above that there are > already up to 20 host events on some devices even if only 8 are connected to the MCU. We've already discussed this with Suman: it is unlikely that HW with more than 8 host interrupts connected to the MCU will arrive. > > > + description: | > > + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC > > + output interrupts 2 through 9) that are not connected to the Arm interrupt > > + controller or are shared and used by other devices or processors in the > > + SoC. Define this property when any of 8 interrupts should not be handled > > + by Arm interrupt controller. > > + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt > > + connected to MPU > > + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and > > + "host_intr7" interrupts connected to MPU, and other ICSSG > > + instances. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-names > > + - interrupt-controller > > + - "#interrupt-cells" > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + /* AM33xx PRU-ICSS */ > > + pruss: pruss@0 { > > + compatible = "ti,am3356-pruss"; > > + reg = <0x0 0x80000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + pruss_intc: interrupt-controller@20000 { > > + compatible = "ti,pruss-intc"; > > + reg = <0x20000 0x2000>; > > + interrupts = <20 21 22 23 24 25 26 27>; > > + interrupt-names = "host_intr0", "host_intr1", > > + "host_intr2", "host_intr3", > > + "host_intr4", "host_intr5", > > + "host_intr6", "host_intr7"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + }; > > + }; > > + > > + - | > > + > > + /* AM4376 PRU-ICSS */ > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + pruss@0 { > > + compatible = "ti,am4376-pruss"; > > + reg = <0x0 0x40000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + interrupt-controller@20000 { > > + compatible = "ti,pruss-intc"; > > + reg = <0x20000 0x2000>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "host_intr0", "host_intr1", > > + "host_intr2", "host_intr3", > > + "host_intr4", > > + "host_intr6", "host_intr7"; > > + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ > > Is 0b00100000 valid syntax in device tree (instead of 0x20 + comment)? Actually I think more readable will be to define and use BIT() directly. Similar to what is done for one of the omap dtsi: https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/omap3-gta04.dtsi#L648 Thank you for your review, Grzegorz
On 7/31/20 6:48 AM, Grzegorz Jaszczyk wrote: > On Wed, 29 Jul 2020 at 19:34, David Lechner <david@lechnology.com> wrote: >> It is not clear what the meaning of each cell is. Looking at later patches, it >> looks like the first cell is the PRU system event number, the second cell is the >> channel and the third cell is the host event number. > > Ok, how about updating above description like this: > Client users shall use the PRU System event number (the interrupt source > that the client is interested in) [cell 1], PRU channel [cell 2] and PRU > host_intr (target) [cell 3] as the value of the interrupts property in their > node. The system events can be mapped to some output host interrupts through 2 > levels of many-to-one mapping i.e. events to channel mapping and channels to > host interrupts so through this property entire mapping is provided. Cell 3 is host_intr0-7? How would we map to other host events?
On Fri, Jul 31, 2020 at 01:48:57PM +0200, Grzegorz Jaszczyk wrote: > On Wed, 29 Jul 2020 at 19:34, David Lechner <david@lechnology.com> wrote: > > > > On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > > > From: Suman Anna <s-anna@ti.com> > > > > > > The Programmable Real-Time Unit and Industrial Communication Subsystem > > > (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that > > > can handle various system input events and post interrupts back to the > > > device-level initiators. The INTC can support upto 64 input events on > > > > nit: "up to" is two separate words > > Ok. > > > > > > most SoCs with individual control configuration and h/w prioritization. > > > These events are mapped onto 10 output interrupt lines through two levels > > > of many-to-one mapping support. Different interrupt lines are routed to > > > the individual PRU cores or to the host CPU or to other PRUSS instances. > > > > > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > > > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > > > a higher number of host interrupts (20 vs 10) and can handle an increased > > > number of input events (160 vs 64) from various SoC interrupt sources. > > > > > > Add the bindings document for these interrupt controllers on all the > > > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > > > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > > > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > > > and J721E SoCs. > > > > > > Signed-off-by: Suman Anna <s-anna@ti.com> > > > Signed-off-by: Andrew F. Davis <afd@ti.com> > > > Signed-off-by: Roger Quadros <rogerq@ti.com> > > > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > > > --- > > > v3->v4: > > > - Drop allOf references to interrupt-controller.yaml and > > > interrupts.yaml. > > > - Drop items descriptions and use only maxItems: 1 as suggested by Rob. > > > - Convert irqs-reserved property from uint8-array to bitmask. > > > - Minor descriptions updates. > > > - Change interrupt-cells to 3 in order to provide 2-level mapping > > > description for interrupts routed to the main CPU (as Marc requested). > > > - Merge the irqs-reserved and irqs-shared to one property since they > > > can be handled by one logic. > > > - Drop reviewed-by due to introduced changes. > > > - Add another example illustrating irqs-reserved property usage. > > > v2->v3: > > > - Convert dt-binding to YAML > > > v1->v2: > > > - https://patchwork.kernel.org/patch/11069767/ > > > --- > > > .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++++++++++++++++++ > > > 1 file changed, 157 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > new file mode 100644 > > > index 0000000..7336b11 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > @@ -0,0 +1,157 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: TI PRU-ICSS Local Interrupt Controller > > > + > > > +maintainers: > > > + - Suman Anna <s-anna@ti.com> > > > + > > > +description: | > > > + Each PRU-ICSS has a single interrupt controller instance that is common > > > + to all the PRU cores. Most interrupt controllers can route 64 input events > > > + which are then mapped to 10 possible output interrupts through two levels > > > + of mapping. The input events can be triggered by either the PRUs and/or > > > + various other PRUSS internal and external peripherals. The first 2 output > > > + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the > > > + remaining 8 (2 through 9) connected to external interrupt controllers > > > + including the MPU and/or other PRUSS instances, DSPs or devices. > > > + > > > + The property "ti,irqs-reserved" is used for denoting the connection > > > + differences on the output interrupts 2 through 9. If this property is not > > > + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 > > > + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt > > > + controller. > > > + > > > + The K3 family of SoCs can handle 160 input events that can be mapped to 20 > > > + different possible output interrupts. The additional output interrupts (10 > > > + through 19) are connected to new sub-modules within the ICSSG instances. > > > + > > > + This interrupt-controller node should be defined as a child node of the > > > + corresponding PRUSS node. The node should be named "interrupt-controller". > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - ti,pruss-intc > > > + - ti,icssg-intc > > > + description: | > > > + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, > > > + AM335x family of SoCs, > > > + AM437x family of SoCs, > > > + AM57xx family of SoCs > > > + 66AK2G family of SoCs > > > + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + minItems: 1 > > > + maxItems: 8 > > > + description: | > > > + All the interrupts generated towards the main host processor in the SoC. > > > + A shared interrupt can be skipped if the desired destination and usage is > > > + by a different processor/device. > > > > This sounds like using device tree for configuration. Also, isn't this what the > > ti,irqs-reserved property is for? > > Yes this is what ti,irqs-reserved is also used for. The intention was > to keep both in sync, so it would be less confusing: if some > interrupts are on irqs-reserved list, they shouldn't be present here. > In terms of shared interrupt usage I will not call it configuration > via device-tree, rather design description (for single device tree > description given shared interrupt is used or as MCPU one or as > different processor/device one). > > > > > > + > > > + interrupt-names: > > > + minItems: 1 > > > + maxItems: 8 > > > + items: > > > + pattern: host_intr[0-7] > > > + description: | > > > + Should use one of the above names for each valid host event interrupt > > > + connected to Arm interrupt controller, the name should match the > > > + corresponding host event interrupt number. > > > + > > > + interrupt-controller: true > > > + > > > + "#interrupt-cells": > > > + const: 3 > > > + description: | > > > + Client users shall use the PRU System event number (the interrupt source > > > + that the client is interested in), PRU channel and PRU host_intr (target) > > > + as the value of the interrupts property in their node. The system events > > > + can be mapped to some output host interrupts through 2 levels of > > > + many-to-one mapping i.e. events to channel mapping and channels to host > > > + interrupts so through this property entire mapping is provided. > > > > It is not clear what the meaning of each cell is. Looking at later patches, it > > looks like the first cell is the PRU system event number, the second cell is the > > channel and the third cell is the host event number. > > Ok, how about updating above description like this: > Client users shall use the PRU System event number (the interrupt source > that the client is interested in) [cell 1], PRU channel [cell 2] and PRU > host_intr (target) [cell 3] as the value of the interrupts property in their > node. The system events can be mapped to some output host interrupts through 2 > levels of many-to-one mapping i.e. events to channel mapping and channels to > host interrupts so through this property entire mapping is provided. > > > > > > + > > > + ti,irqs-reserved: > > > + $ref: /schemas/types.yaml#definitions/uint8 > > > > Is 8 bits enough for any possible future devices? It is written above that there are > > already up to 20 host events on some devices even if only 8 are connected to the MCU. > > We've already discussed this with Suman: it is unlikely that HW with > more than 8 host interrupts connected to the MCU will arrive. > > > > > > + description: | > > > + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC > > > + output interrupts 2 through 9) that are not connected to the Arm interrupt > > > + controller or are shared and used by other devices or processors in the > > > + SoC. Define this property when any of 8 interrupts should not be handled > > > + by Arm interrupt controller. > > > + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt > > > + connected to MPU > > > + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and > > > + "host_intr7" interrupts connected to MPU, and other ICSSG > > > + instances. > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - interrupt-names > > > + - interrupt-controller > > > + - "#interrupt-cells" > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + /* AM33xx PRU-ICSS */ > > > + pruss: pruss@0 { > > > + compatible = "ti,am3356-pruss"; > > > + reg = <0x0 0x80000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + ranges; > > > + > > > + pruss_intc: interrupt-controller@20000 { > > > + compatible = "ti,pruss-intc"; > > > + reg = <0x20000 0x2000>; > > > + interrupts = <20 21 22 23 24 25 26 27>; > > > + interrupt-names = "host_intr0", "host_intr1", > > > + "host_intr2", "host_intr3", > > > + "host_intr4", "host_intr5", > > > + "host_intr6", "host_intr7"; > > > + interrupt-controller; > > > + #interrupt-cells = <3>; > > > + }; > > > + }; > > > + > > > + - | > > > + > > > + /* AM4376 PRU-ICSS */ > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > + pruss@0 { > > > + compatible = "ti,am4376-pruss"; > > > + reg = <0x0 0x40000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + ranges; > > > + > > > + interrupt-controller@20000 { > > > + compatible = "ti,pruss-intc"; > > > + reg = <0x20000 0x2000>; > > > + interrupt-controller; > > > + #interrupt-cells = <3>; > > > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "host_intr0", "host_intr1", > > > + "host_intr2", "host_intr3", > > > + "host_intr4", > > > + "host_intr6", "host_intr7"; > > > + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ > > > > Is 0b00100000 valid syntax in device tree (instead of 0x20 + comment)? Using binary? No. > Actually I think more readable will be to define and use BIT() > directly. Similar to what is done for one of the omap dtsi: > https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/omap3-gta04.dtsi#L648 No, please don't add/use BIT(). I'd assume the common case here is not only 1 bit set. Even if it is here, it's not in general, and I just don't want more macros. Rob
On Fri, 31 Jul 2020 at 23:09, Rob Herring <robh@kernel.org> wrote: > > On Fri, Jul 31, 2020 at 01:48:57PM +0200, Grzegorz Jaszczyk wrote: > > On Wed, 29 Jul 2020 at 19:34, David Lechner <david@lechnology.com> wrote: > > > > > > On 7/28/20 4:18 AM, Grzegorz Jaszczyk wrote: > > > > From: Suman Anna <s-anna@ti.com> > > > > > > > > The Programmable Real-Time Unit and Industrial Communication Subsystem > > > > (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that > > > > can handle various system input events and post interrupts back to the > > > > device-level initiators. The INTC can support upto 64 input events on > > > > > > nit: "up to" is two separate words > > > > Ok. > > > > > > > > > most SoCs with individual control configuration and h/w prioritization. > > > > These events are mapped onto 10 output interrupt lines through two levels > > > > of many-to-one mapping support. Different interrupt lines are routed to > > > > the individual PRU cores or to the host CPU or to other PRUSS instances. > > > > > > > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > > > > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > > > > a higher number of host interrupts (20 vs 10) and can handle an increased > > > > number of input events (160 vs 64) from various SoC interrupt sources. > > > > > > > > Add the bindings document for these interrupt controllers on all the > > > > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > > > > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > > > > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > > > > and J721E SoCs. > > > > > > > > Signed-off-by: Suman Anna <s-anna@ti.com> > > > > Signed-off-by: Andrew F. Davis <afd@ti.com> > > > > Signed-off-by: Roger Quadros <rogerq@ti.com> > > > > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> > > > > --- > > > > v3->v4: > > > > - Drop allOf references to interrupt-controller.yaml and > > > > interrupts.yaml. > > > > - Drop items descriptions and use only maxItems: 1 as suggested by Rob. > > > > - Convert irqs-reserved property from uint8-array to bitmask. > > > > - Minor descriptions updates. > > > > - Change interrupt-cells to 3 in order to provide 2-level mapping > > > > description for interrupts routed to the main CPU (as Marc requested). > > > > - Merge the irqs-reserved and irqs-shared to one property since they > > > > can be handled by one logic. > > > > - Drop reviewed-by due to introduced changes. > > > > - Add another example illustrating irqs-reserved property usage. > > > > v2->v3: > > > > - Convert dt-binding to YAML > > > > v1->v2: > > > > - https://patchwork.kernel.org/patch/11069767/ > > > > --- > > > > .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++++++++++++++++++ > > > > 1 file changed, 157 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > > new file mode 100644 > > > > index 0000000..7336b11 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > > > > @@ -0,0 +1,157 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: TI PRU-ICSS Local Interrupt Controller > > > > + > > > > +maintainers: > > > > + - Suman Anna <s-anna@ti.com> > > > > + > > > > +description: | > > > > + Each PRU-ICSS has a single interrupt controller instance that is common > > > > + to all the PRU cores. Most interrupt controllers can route 64 input events > > > > + which are then mapped to 10 possible output interrupts through two levels > > > > + of mapping. The input events can be triggered by either the PRUs and/or > > > > + various other PRUSS internal and external peripherals. The first 2 output > > > > + interrupts (0, 1) are fed exclusively to the internal PRU cores, with the > > > > + remaining 8 (2 through 9) connected to external interrupt controllers > > > > + including the MPU and/or other PRUSS instances, DSPs or devices. > > > > + > > > > + The property "ti,irqs-reserved" is used for denoting the connection > > > > + differences on the output interrupts 2 through 9. If this property is not > > > > + defined, it implies that all the PRUSS INTC output interrupts 2 through 9 > > > > + (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt > > > > + controller. > > > > + > > > > + The K3 family of SoCs can handle 160 input events that can be mapped to 20 > > > > + different possible output interrupts. The additional output interrupts (10 > > > > + through 19) are connected to new sub-modules within the ICSSG instances. > > > > + > > > > + This interrupt-controller node should be defined as a child node of the > > > > + corresponding PRUSS node. The node should be named "interrupt-controller". > > > > + > > > > +properties: > > > > + compatible: > > > > + enum: > > > > + - ti,pruss-intc > > > > + - ti,icssg-intc > > > > + description: | > > > > + Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, > > > > + AM335x family of SoCs, > > > > + AM437x family of SoCs, > > > > + AM57xx family of SoCs > > > > + 66AK2G family of SoCs > > > > + Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + interrupts: > > > > + minItems: 1 > > > > + maxItems: 8 > > > > + description: | > > > > + All the interrupts generated towards the main host processor in the SoC. > > > > + A shared interrupt can be skipped if the desired destination and usage is > > > > + by a different processor/device. > > > > > > This sounds like using device tree for configuration. Also, isn't this what the > > > ti,irqs-reserved property is for? > > > > Yes this is what ti,irqs-reserved is also used for. The intention was > > to keep both in sync, so it would be less confusing: if some > > interrupts are on irqs-reserved list, they shouldn't be present here. > > In terms of shared interrupt usage I will not call it configuration > > via device-tree, rather design description (for single device tree > > description given shared interrupt is used or as MCPU one or as > > different processor/device one). > > > > > > > > > + > > > > + interrupt-names: > > > > + minItems: 1 > > > > + maxItems: 8 > > > > + items: > > > > + pattern: host_intr[0-7] > > > > + description: | > > > > + Should use one of the above names for each valid host event interrupt > > > > + connected to Arm interrupt controller, the name should match the > > > > + corresponding host event interrupt number. > > > > + > > > > + interrupt-controller: true > > > > + > > > > + "#interrupt-cells": > > > > + const: 3 > > > > + description: | > > > > + Client users shall use the PRU System event number (the interrupt source > > > > + that the client is interested in), PRU channel and PRU host_intr (target) > > > > + as the value of the interrupts property in their node. The system events > > > > + can be mapped to some output host interrupts through 2 levels of > > > > + many-to-one mapping i.e. events to channel mapping and channels to host > > > > + interrupts so through this property entire mapping is provided. > > > > > > It is not clear what the meaning of each cell is. Looking at later patches, it > > > looks like the first cell is the PRU system event number, the second cell is the > > > channel and the third cell is the host event number. > > > > Ok, how about updating above description like this: > > Client users shall use the PRU System event number (the interrupt source > > that the client is interested in) [cell 1], PRU channel [cell 2] and PRU > > host_intr (target) [cell 3] as the value of the interrupts property in their > > node. The system events can be mapped to some output host interrupts through 2 > > levels of many-to-one mapping i.e. events to channel mapping and channels to > > host interrupts so through this property entire mapping is provided. > > > > > > > > > + > > > > + ti,irqs-reserved: > > > > + $ref: /schemas/types.yaml#definitions/uint8 > > > > > > Is 8 bits enough for any possible future devices? It is written above that there are > > > already up to 20 host events on some devices even if only 8 are connected to the MCU. > > > > We've already discussed this with Suman: it is unlikely that HW with > > more than 8 host interrupts connected to the MCU will arrive. > > > > > > > > > + description: | > > > > + Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC > > > > + output interrupts 2 through 9) that are not connected to the Arm interrupt > > > > + controller or are shared and used by other devices or processors in the > > > > + SoC. Define this property when any of 8 interrupts should not be handled > > > > + by Arm interrupt controller. > > > > + Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt > > > > + connected to MPU > > > > + - AM65x and J721E SoCs have "host_intr5", "host_intr6" and > > > > + "host_intr7" interrupts connected to MPU, and other ICSSG > > > > + instances. > > > > + > > > > +required: > > > > + - compatible > > > > + - reg > > > > + - interrupts > > > > + - interrupt-names > > > > + - interrupt-controller > > > > + - "#interrupt-cells" > > > > + > > > > +additionalProperties: false > > > > + > > > > +examples: > > > > + - | > > > > + /* AM33xx PRU-ICSS */ > > > > + pruss: pruss@0 { > > > > + compatible = "ti,am3356-pruss"; > > > > + reg = <0x0 0x80000>; > > > > + #address-cells = <1>; > > > > + #size-cells = <1>; > > > > + ranges; > > > > + > > > > + pruss_intc: interrupt-controller@20000 { > > > > + compatible = "ti,pruss-intc"; > > > > + reg = <0x20000 0x2000>; > > > > + interrupts = <20 21 22 23 24 25 26 27>; > > > > + interrupt-names = "host_intr0", "host_intr1", > > > > + "host_intr2", "host_intr3", > > > > + "host_intr4", "host_intr5", > > > > + "host_intr6", "host_intr7"; > > > > + interrupt-controller; > > > > + #interrupt-cells = <3>; > > > > + }; > > > > + }; > > > > + > > > > + - | > > > > + > > > > + /* AM4376 PRU-ICSS */ > > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > > + pruss@0 { > > > > + compatible = "ti,am4376-pruss"; > > > > + reg = <0x0 0x40000>; > > > > + #address-cells = <1>; > > > > + #size-cells = <1>; > > > > + ranges; > > > > + > > > > + interrupt-controller@20000 { > > > > + compatible = "ti,pruss-intc"; > > > > + reg = <0x20000 0x2000>; > > > > + interrupt-controller; > > > > + #interrupt-cells = <3>; > > > > + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > > > > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > > > > + interrupt-names = "host_intr0", "host_intr1", > > > > + "host_intr2", "host_intr3", > > > > + "host_intr4", > > > > + "host_intr6", "host_intr7"; > > > > + ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ > > > > > > Is 0b00100000 valid syntax in device tree (instead of 0x20 + comment)? > > Using binary? No. > > > Actually I think more readable will be to define and use BIT() > > directly. Similar to what is done for one of the omap dtsi: > > https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/omap3-gta04.dtsi#L648 > > No, please don't add/use BIT(). I'd assume the common case here is not > only 1 bit set. Even if it is here, it's not in general, and I just > don't want more macros. > Ok, so I will leave it as is. Thank you, Grzegorz
Hi All, The following is a v4 version of the series [1][2][3] that adds an IRQChip driver for the local interrupt controller present within a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs. Please see the v1 cover-letter [1] for details about the features of this interrupt controller. More details can be found in any of the supported SoC TRMs. Eg: Chapter 30.1.6 of AM5728 TRM [4] Please see the individual patches for exact changes in each patch, following are the main changes from v3: - Change interrupt-cells to 3 in order to provide 2-level mapping description in DT for interrupts routed to the main CPU as Marc requested (patch #1 and patch #2). - Get rid of the two distinct code paths in the xlate function and allow to proceed only with 3 parameters description as Marc suggested (patch #2). - Due to above modification squash patch #6 of previous patchset into patch #2. - Merge the irqs-reserved and irqs-shared to one property (patch #1 and #2). [1] https://patchwork.kernel.org/cover/11034561/ [2] https://patchwork.kernel.org/cover/11069749/ [3] https://patchwork.kernel.org/cover/11639055/ [4] http://www.ti.com/lit/pdf/spruhz6 Best regards Grzegorz David Lechner (1): irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk (1): irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Suman Anna (3): dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings irqchip/irq-pruss-intc: Add logic for handling reserved interrupts irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs .../interrupt-controller/ti,pruss-intc.yaml | 157 +++++ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 659 +++++++++++++++++++++ 4 files changed, 827 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml create mode 100644 drivers/irqchip/irq-pruss-intc.c -- 2.7.4