diff mbox series

[v1,05/10] mips: Rename CONFIG_CPU_CAVIUM_OCTEON to CONFIG_CPU_MIPS64_OCTEON

Message ID 20200502085944.13444-6-sr@denx.de
State New
Headers show
Series mips: Add initial Octeon MIPS64 base support | expand

Commit Message

Stefan Roese May 2, 2020, 8:59 a.m. UTC
With the introduction of the MIPS Octeon support, lets use the newly
added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
references completely with this patch.

Signed-off-by: Stefan Roese <sr at denx.de>
---

 arch/mips/include/asm/io.h     | 4 ++--
 arch/mips/include/asm/ptrace.h | 2 +-
 scripts/config_whitelist.txt   | 1 -
 3 files changed, 3 insertions(+), 4 deletions(-)

Comments

Daniel Schwierzeck May 13, 2020, 1:16 p.m. UTC | #1
Am 02.05.20 um 10:59 schrieb Stefan Roese:
> With the introduction of the MIPS Octeon support, lets use the newly
> added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
> CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
> references completely with this patch.

please keep that symbol, otherwise it complicates future header file
syncs with Linux (currently I'm working on one). You could simply add
CONFIG_CPU_CAVIUM_OCTEON as hidden Kconfig symbol and select it from
CONFIG_CPU_MIPS64_OCTEON

> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> ---
> 
>  arch/mips/include/asm/io.h     | 4 ++--
>  arch/mips/include/asm/ptrace.h | 2 +-
>  scripts/config_whitelist.txt   | 1 -
>  3 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 7c40e415c7..072d1718c9 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -223,7 +223,7 @@ static inline void iounmap(const volatile void __iomem *addr)
>  	plat_iounmap(addr);
>  }
>  
> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>  #define war_octeon_io_reorder_wmb()		wmb()
>  #else
>  #define war_octeon_io_reorder_wmb()		do { } while (0)
> @@ -452,7 +452,7 @@ BUILDSTRING(q, u64)
>  #endif
>  
>  
> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>  #define mmiowb() wmb()
>  #else
>  /* Depends on MIPS II instruction set */
> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
> index cb88d6d4f9..60f50450d4 100644
> --- a/arch/mips/include/asm/ptrace.h
> +++ b/arch/mips/include/asm/ptrace.h
> @@ -36,7 +36,7 @@ struct pt_regs {
>  	unsigned long cp0_badvaddr;
>  	unsigned long cp0_cause;
>  	unsigned long cp0_epc;
> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>  	unsigned long long mpl[6];        /* MTM{0-5} */
>  	unsigned long long mtp[6];        /* MTP{0-5} */
>  #endif
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index 7a5da9d822..303a23fdd1 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM
>  CONFIG_CPLD_OR_PRELIM
>  CONFIG_CPM2
>  CONFIG_CPU_ARMV8
> -CONFIG_CPU_CAVIUM_OCTEON
>  CONFIG_CPU_FREQ_HZ
>  CONFIG_CPU_HAS_LLSC
>  CONFIG_CPU_HAS_PREFETCH
>
Stefan Roese May 14, 2020, 8:36 a.m. UTC | #2
On 13.05.20 15:16, Daniel Schwierzeck wrote:
> 
> 
> Am 02.05.20 um 10:59 schrieb Stefan Roese:
>> With the introduction of the MIPS Octeon support, lets use the newly
>> added Kconfig symbol CONFIG_CPU_MIPS64_OCTEON instead of the old Linux
>> CONFIG_CPU_CAVIUM_OCTEON one (which was never set). Remove these
>> references completely with this patch.
> 
> please keep that symbol, otherwise it complicates future header file
> syncs with Linux (currently I'm working on one). You could simply add
> CONFIG_CPU_CAVIUM_OCTEON as hidden Kconfig symbol and select it from
> CONFIG_CPU_MIPS64_OCTEON

Done in v2.

Thanks,
Stefan

>>
>> Signed-off-by: Stefan Roese <sr at denx.de>
>> ---
>>
>>   arch/mips/include/asm/io.h     | 4 ++--
>>   arch/mips/include/asm/ptrace.h | 2 +-
>>   scripts/config_whitelist.txt   | 1 -
>>   3 files changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
>> index 7c40e415c7..072d1718c9 100644
>> --- a/arch/mips/include/asm/io.h
>> +++ b/arch/mips/include/asm/io.h
>> @@ -223,7 +223,7 @@ static inline void iounmap(const volatile void __iomem *addr)
>>   	plat_iounmap(addr);
>>   }
>>   
>> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
>> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>>   #define war_octeon_io_reorder_wmb()		wmb()
>>   #else
>>   #define war_octeon_io_reorder_wmb()		do { } while (0)
>> @@ -452,7 +452,7 @@ BUILDSTRING(q, u64)
>>   #endif
>>   
>>   
>> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
>> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>>   #define mmiowb() wmb()
>>   #else
>>   /* Depends on MIPS II instruction set */
>> diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
>> index cb88d6d4f9..60f50450d4 100644
>> --- a/arch/mips/include/asm/ptrace.h
>> +++ b/arch/mips/include/asm/ptrace.h
>> @@ -36,7 +36,7 @@ struct pt_regs {
>>   	unsigned long cp0_badvaddr;
>>   	unsigned long cp0_cause;
>>   	unsigned long cp0_epc;
>> -#ifdef CONFIG_CPU_CAVIUM_OCTEON
>> +#ifdef CONFIG_CPU_MIPS64_OCTEON
>>   	unsigned long long mpl[6];        /* MTM{0-5} */
>>   	unsigned long long mtp[6];        /* MTP{0-5} */
>>   #endif
>> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
>> index 7a5da9d822..303a23fdd1 100644
>> --- a/scripts/config_whitelist.txt
>> +++ b/scripts/config_whitelist.txt
>> @@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM
>>   CONFIG_CPLD_OR_PRELIM
>>   CONFIG_CPM2
>>   CONFIG_CPU_ARMV8
>> -CONFIG_CPU_CAVIUM_OCTEON
>>   CONFIG_CPU_FREQ_HZ
>>   CONFIG_CPU_HAS_LLSC
>>   CONFIG_CPU_HAS_PREFETCH
>>
> 


Viele Gr??e,
Stefan
diff mbox series

Patch

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 7c40e415c7..072d1718c9 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -223,7 +223,7 @@  static inline void iounmap(const volatile void __iomem *addr)
 	plat_iounmap(addr);
 }
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
 #define war_octeon_io_reorder_wmb()		wmb()
 #else
 #define war_octeon_io_reorder_wmb()		do { } while (0)
@@ -452,7 +452,7 @@  BUILDSTRING(q, u64)
 #endif
 
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
 #define mmiowb() wmb()
 #else
 /* Depends on MIPS II instruction set */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cb88d6d4f9..60f50450d4 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -36,7 +36,7 @@  struct pt_regs {
 	unsigned long cp0_badvaddr;
 	unsigned long cp0_cause;
 	unsigned long cp0_epc;
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#ifdef CONFIG_CPU_MIPS64_OCTEON
 	unsigned long long mpl[6];        /* MTM{0-5} */
 	unsigned long long mtp[6];        /* MTP{0-5} */
 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 7a5da9d822..303a23fdd1 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -234,7 +234,6 @@  CONFIG_CPLD_BR_PRELIM
 CONFIG_CPLD_OR_PRELIM
 CONFIG_CPM2
 CONFIG_CPU_ARMV8
-CONFIG_CPU_CAVIUM_OCTEON
 CONFIG_CPU_FREQ_HZ
 CONFIG_CPU_HAS_LLSC
 CONFIG_CPU_HAS_PREFETCH