@@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+choice
+ prompt "Select the ARM data write cache policy"
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+ TARGET_BCMNSP || CPU_PXA || RZA1
+ default SYS_ARM_CACHE_WRITEBACK
+
+config SYS_ARM_CACHE_WRITEBACK
+ bool "Write-back (WB)"
+ help
+ A write updates the cache only and marks the cache line as dirty.
+ External memory is updated only when the line is evicted or explicitly
+ cleaned.
+
+config SYS_ARM_CACHE_WRITETHROUGH
+ bool "Write-through (WT)"
+ help
+ A write updates both the cache and the external memory system.
+ This does not mark the cache line as dirty.
+
+config SYS_ARM_CACHE_WRITEALLOC
+ bool "Write allocation (WA)"
+ help
+ A cache line is allocated on a write miss. This means that executing a
+ store instruction on the processor might cause a burst read to occur.
+ There is a linefill to obtain the data for the cache line, before the
+ write is performed.
+endchoice
+
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
@@ -10,7 +10,6 @@
/* Architecture, CPU, chip, etc */
#define CONFIG_IPROC
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* Memory Info */
#define CONFIG_SYS_SDRAM_BASE 0x61000000
@@ -16,7 +16,6 @@
/* Miscellaneous */
#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_CMDLINE_TAG
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
@@ -8,8 +8,6 @@
#ifndef __CONFIG_PXA_COMMON_H__
#define __CONFIG_PXA_COMMON_H__
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
/*
* KGDB
*/
@@ -1773,7 +1773,6 @@ CONFIG_SYS_AMASK4
CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK7
-CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
CONFIG_SYS_AT91_PLLA
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py. Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK (the default configuration). The patch also avoids to select simultaneously 2 configurations. Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com> --- Changes in v2: - default SYS_ARM_CACHE_WRITETHROUGH if CPU_PXA || RZA1 and remove defconfig impacts for grpeach and colibri_pxa270 arch/arm/Kconfig | 28 +++++++++++++++++++++ arch/arm/include/asm/iproc-common/configs.h | 1 - include/configs/grpeach.h | 1 - include/configs/pxa-common.h | 2 -- scripts/config_whitelist.txt | 1 - 5 files changed, 28 insertions(+), 5 deletions(-)