| Message ID | 20200330171926.26119-1-marek.behun@nic.cz |
|---|---|
| State | Accepted |
| Commit | b80ca8176dc0e78d3fb22b2389c847a5d96ee583 |
| Headers | show |
| Series | [u-boot-marvell,1/4] arm: mvebu: turris_mox: Fix early SPI communication | expand |
Hi Marek, On 30.03.20 19:19, Marek Beh?n wrote: > The SPI clock signal changes value when the SPI configuration register > is configured. This can sometimes lead to the device misinterpreting > the enablement of the SPI controller as actual clock tick. > This can be solved by first setting the SPI CS1 pin from GPIO to SPI mode, > and only after that writing the SPI configuration register. > > Signed-off-by: Marek Beh?n <marek.behun at nic.cz> > --- > board/CZ.NIC/turris_mox/turris_mox.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c > index 377191baef..7118096f32 100644 > --- a/board/CZ.NIC/turris_mox/turris_mox.c > +++ b/board/CZ.NIC/turris_mox/turris_mox.c > @@ -67,9 +67,9 @@ int board_fix_fdt(void *blob) > * to read SPI by reading/writing SPI registers directly > */ > > - writel(0x563fa, ARMADA_37XX_NB_GPIO_SEL); > writel(0x10df, ARMADA_37XX_SPI_CFG); > - writel(0x2005b, ARMADA_37XX_SPI_CTRL); > + clrbits_le32(ARMADA_37XX_NB_GPIO_SEL, BIT(12)); > + setbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17)); > > while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2)) > udelay(1); > @@ -89,7 +89,7 @@ int board_fix_fdt(void *blob) > > size = i; > > - writel(0x5b, ARMADA_37XX_SPI_CTRL); > + clrbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17)); Could you please add some comments to those bit manipulations above? I know it was not there before. But please add something like the commit text here, explaining what this code is doing and why. Thanks, Stefan
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 377191baef..7118096f32 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -67,9 +67,9 @@ int board_fix_fdt(void *blob) * to read SPI by reading/writing SPI registers directly */ - writel(0x563fa, ARMADA_37XX_NB_GPIO_SEL); writel(0x10df, ARMADA_37XX_SPI_CFG); - writel(0x2005b, ARMADA_37XX_SPI_CTRL); + clrbits_le32(ARMADA_37XX_NB_GPIO_SEL, BIT(12)); + setbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17)); while (!(readl(ARMADA_37XX_SPI_CTRL) & 0x2)) udelay(1); @@ -89,7 +89,7 @@ int board_fix_fdt(void *blob) size = i; - writel(0x5b, ARMADA_37XX_SPI_CTRL); + clrbits_le32(ARMADA_37XX_SPI_CTRL, BIT(17)); if (size > 1 && (topology[1] == MOX_MODULE_PCI || topology[1] == MOX_MODULE_USB3 ||
The SPI clock signal changes value when the SPI configuration register is configured. This can sometimes lead to the device misinterpreting the enablement of the SPI controller as actual clock tick. This can be solved by first setting the SPI CS1 pin from GPIO to SPI mode, and only after that writing the SPI configuration register. Signed-off-by: Marek Beh?n <marek.behun at nic.cz> --- board/CZ.NIC/turris_mox/turris_mox.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)