diff mbox series

[8/9] ram: stm32mp1: reduce delay after BIST reset for tuning

Message ID 20200306111355.8.I2ed443e2c15db6b007f836254b3753da9b06e76d@changeid
State Accepted
Commit d424e6786f637d3181ffa9e2cc9ed6bca00aa30f
Headers show
Series ram: stm32mp1: fixes | expand

Commit Message

Patrick Delaunay March 6, 2020, 10:14 a.m. UTC
Reduce the delay after BIST delay, from 1ms to 10us
which is enough accoriding datasheet.

Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
---

 drivers/ram/stm32mp1/stm32mp1_tuning.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Patrice CHOTARD March 18, 2020, 9:46 a.m. UTC | #1
On 3/6/20 11:14 AM, Patrick Delaunay wrote:
> Reduce the delay after BIST delay, from 1ms to 10us
> which is enough accoriding datasheet.
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
>
>  drivers/ram/stm32mp1/stm32mp1_tuning.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
> index 07d57d496c..3013b7b667 100644
> --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
> +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
> @@ -402,7 +402,7 @@ run:
>  		writel(rand(), &phy->bistlsr);
>  
>  	/* some delay to reset BIST */
> -	mdelay(1);
> +	udelay(10);
>  
>  	/*Perform BIST Run*/
>  	clrsetbits_le32(&phy->bistrr,

Acked-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

Patrice
Patrick Delaunay March 24, 2020, 8:51 a.m. UTC | #2
Hi,

> From: Patrick DELAUNAY <patrick.delaunay at st.com>
> Sent: vendredi 6 mars 2020 11:14
> 
> Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding
> datasheet.
> 
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---

Applied to u-boot-stm/next, thanks!

Regards

Patrick
diff mbox series

Patch

diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
index 07d57d496c..3013b7b667 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
@@ -402,7 +402,7 @@  run:
 		writel(rand(), &phy->bistlsr);
 
 	/* some delay to reset BIST */
-	mdelay(1);
+	udelay(10);
 
 	/*Perform BIST Run*/
 	clrsetbits_le32(&phy->bistrr,