Message ID | 1584387649-20959-6-git-send-email-twarren@nvidia.com |
---|---|
State | New |
Headers | show |
Series | Misc fixes for Tegra | expand |
On 3/16/20 1:40 PM, twarren at nvidia.com wrote: > From: Tom Warren <twarren at nvidia.com> > > Large kernels (>32MB) can fail to boot because they overwrite the FDT > address, corrupting the DTB. Stephen Warren had created a fix to > dynamically adjust the fdt/ramdisk/pxefile/kernel addr vars at boot time > for T186, which allows a large kernel to load and boot. That was actually done to support holes in the RAM map; it's not actually required in order to support large kernels at all. We could just as easily directly modify the existing hard-coded load addresses. > This is based on his commit, but applied to the tegraXXX-common.h > headers so it's used on all T186 and T210 Jetson boards. Note that I've > put the kernel 'size' param at 0x03000000, or 48MB, to leave room for > kernel growth. Current L4T kernels are running at about 32MB. I had completely forgotten that we had the calculated env vars feature upstream already! I thought we went with 96 or 128MB space for the kernel downstream, to make sure there'd "never" any future problem as the kernel grows? But this patch seems OK for now I guess.
-----Original Message----- From: Stephen Warren <swarren at wwwdotorg.org> Sent: Tuesday, March 17, 2020 10:38 AM To: Tom Warren <TWarren at nvidia.com> Cc: u-boot at lists.denx.de Subject: Re: [PATCH 5/5] ARM: Tegra: Use calc env var feature on all boards External email: Use caution opening links or attachments On 3/16/20 1:40 PM, twarren at nvidia.com wrote: > From: Tom Warren <twarren at nvidia.com> > > Large kernels (>32MB) can fail to boot because they overwrite the FDT > address, corrupting the DTB. Stephen Warren had created a fix to > dynamically adjust the fdt/ramdisk/pxefile/kernel addr vars at boot > time for T186, which allows a large kernel to load and boot. That was actually done to support holes in the RAM map; it's not actually required in order to support large kernels at all. We could just as easily directly modify the existing hard-coded load addresses. > This is based on his commit, but applied to the tegraXXX-common.h > headers so it's used on all T186 and T210 Jetson boards. Note that > I've put the kernel 'size' param at 0x03000000, or 48MB, to leave room > for kernel growth. Current L4T kernels are running at about 32MB. I had completely forgotten that we had the calculated env vars feature upstream already! I thought we went with 96 or 128MB space for the kernel downstream, to make sure there'd "never" any future problem as the kernel grows? But this patch seems OK for now I guess. [Tom] Yes, we have a large (128MB) kernel size in downstream L4T U-Boot, but only because of the need to test GCOV kernels - I didn't think that excessive allocation was required upstream, so I backed it off to 48MB. As to your point about just fixing the hard-coding of the kernel/ramdisk/fdt_addr_r in T210, I can do that, but it seemed more elegant and future-proof to use the calc env vars code you'd added for T186, plus it brings the two builds in sync, using the same allocation strategy for these 'load' vars. ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index 7c6d68a..90d764f 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2013-2016, NVIDIA CORPORATION. + * Copyright (c) 2013-2020, NVIDIA CORPORATION. + * */ #ifndef _P2771_0000_H @@ -17,26 +18,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 2 -#define BOARD_EXTRA_ENV_SETTINGS \ - "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ - "ramdisk_addr_r\0" \ - "kernel_addr_r_align=00200000\0" \ - "kernel_addr_r_offset=00080000\0" \ - "kernel_addr_r_size=02000000\0" \ - "kernel_addr_r_aliases=loadaddr\0" \ - "fdt_addr_r_align=00200000\0" \ - "fdt_addr_r_offset=00000000\0" \ - "fdt_addr_r_size=00200000\0" \ - "scriptaddr_align=00200000\0" \ - "scriptaddr_offset=00000000\0" \ - "scriptaddr_size=00200000\0" \ - "pxefile_addr_r_align=00200000\0" \ - "pxefile_addr_r_offset=00000000\0" \ - "pxefile_addr_r_size=00200000\0" \ - "ramdisk_addr_r_align=00200000\0" \ - "ramdisk_addr_r_offset=00000000\0" \ - "ramdisk_addr_r_size=02000000\0" - #include "tegra-common-post.h" /* Crystal is 38.4MHz. clk_m runs at half that rate */ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index b4936cc..e88e68d 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright 2013-2016, NVIDIA CORPORATION. + * Copyright (c) 2013-2020, NVIDIA CORPORATION. */ #ifndef _TEGRA186_COMMON_H_ @@ -50,6 +50,24 @@ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" + "ramdisk_addr_r=0x82100000\0" \ + "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ + "ramdisk_addr_r\0" \ + "kernel_addr_r_align=00200000\0" \ + "kernel_addr_r_offset=00080000\0" \ + "kernel_addr_r_size=03000000\0" \ + "kernel_addr_r_aliases=loadaddr\0" \ + "fdt_addr_r_align=00200000\0" \ + "fdt_addr_r_offset=00000000\0" \ + "fdt_addr_r_size=00200000\0" \ + "scriptaddr_align=00200000\0" \ + "scriptaddr_offset=00000000\0" \ + "scriptaddr_size=00200000\0" \ + "pxefile_addr_r_align=00200000\0" \ + "pxefile_addr_r_offset=00000000\0" \ + "pxefile_addr_r_size=00200000\0" \ + "ramdisk_addr_r_align=00200000\0" \ + "ramdisk_addr_r_offset=00000000\0" \ + "ramdisk_addr_r_size=02000000\0" #endif diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1c53311..0d15b30 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2013-2020, NVIDIA CORPORATION. */ #ifndef _TEGRA210_COMMON_H_ @@ -47,7 +46,25 @@ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" + "ramdisk_addr_r=0x82100000\0" \ + "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ + "ramdisk_addr_r\0" \ + "kernel_addr_r_align=00200000\0" \ + "kernel_addr_r_offset=00080000\0" \ + "kernel_addr_r_size=03000000\0" \ + "kernel_addr_r_aliases=loadaddr\0" \ + "fdt_addr_r_align=00200000\0" \ + "fdt_addr_r_offset=00000000\0" \ + "fdt_addr_r_size=00200000\0" \ + "scriptaddr_align=00200000\0" \ + "scriptaddr_offset=00000000\0" \ + "scriptaddr_size=00200000\0" \ + "pxefile_addr_r_align=00200000\0" \ + "pxefile_addr_r_offset=00000000\0" \ + "pxefile_addr_r_size=00200000\0" \ + "ramdisk_addr_r_align=00200000\0" \ + "ramdisk_addr_r_offset=00000000\0" \ + "ramdisk_addr_r_size=02000000\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI