| Message ID | fb1225e3-b8fe-3c33-48fd-687a1ca14ad1@ic-automation.de |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: socfpga: Remove socfpga_sdram_apply_static_cfg() | expand |
On 2/6/20 1:57 PM, Nico Becker wrote: > Am 06.02.2020 um 12:53 schrieb Marek Vasut: >> On 2/6/20 11:50 AM, Nico Becker wrote: >>> Hello, >> >> Hi, >> >>> after removing the function socfpga_sdram_apply_static_cfg() in >>> misc_gen5 we can not use the FPGA2SDRAM bridge. >>> >>> Without the apply static cfg the kernel crash every time, >>> if we try to write @ the fpga2sdram bridge. After an soft reset >>> everything is working. >>> >>> If we add the socfpga_sdram_apply_static_cfg() in the >>> u-boot source code, everything is fine. >>> Now we can use the fpga2sdram bridge after power on. >>> >>> Our setup: >>> - u-boot v2020.01 >>> - load and write fpga firmware >>> - enable bridges >>> - boot linux >>> >>> I have found some information at >>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> >>> >>> >>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> >> >> Can you send a patch which fixes this for you, with Fixes: tag ? >> Then it would be clear what you changed. >> >> Thanks >> > > Hello, > the code was removed @ commit c5f4b805. Did you read the commit message of that commit and what problem that was solving ? Clearly, reverting the commit isn't the way to go. We need to find a way to unbreak this for you, while not break other platforms. > I attached my patch, sorry for the format, i am new in this. [...]
Am 06.02.2020 um 14:00 schrieb Marek Vasut: > On 2/6/20 1:57 PM, Nico Becker wrote: >> Am 06.02.2020 um 12:53 schrieb Marek Vasut: >>> On 2/6/20 11:50 AM, Nico Becker wrote: >>>> Hello, >>> >>> Hi, >>> >>>> after removing the function socfpga_sdram_apply_static_cfg() in >>>> misc_gen5 we can not use the FPGA2SDRAM bridge. >>>> >>>> Without the apply static cfg the kernel crash every time, >>>> if we try to write @ the fpga2sdram bridge. After an soft reset >>>> everything is working. >>>> >>>> If we add the socfpga_sdram_apply_static_cfg() in the >>>> u-boot source code, everything is fine. >>>> Now we can use the fpga2sdram bridge after power on. >>>> >>>> Our setup: >>>> - u-boot v2020.01 >>>> - load and write fpga firmware >>>> - enable bridges >>>> - boot linux >>>> >>>> I have found some information at >>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> >>>> >>>> >>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> >>> >>> Can you send a patch which fixes this for you, with Fixes: tag ? >>> Then it would be clear what you changed. >>> >>> Thanks >>> >> >> Hello, >> the code was removed @ commit c5f4b805. > > Did you read the commit message of that commit and what problem that was > solving ? Clearly, reverting the commit isn't the way to go. We need to > find a way to unbreak this for you, while not break other platforms. > >> I attached my patch, sorry for the format, i am new in this. > > [...] > Hi, yes i read the commit message. but i found no other option to enable the sdram bridges, without crashes/hanging up linux, with the removed source code. i ve found some more information @intel <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> Intel talk about an bridge_enable_handoff in my opionion the cmd set the sram aply cfg /* add signle command to enable all bridges based on handoff */ setenv("bridge_enable_handoff", "mw $fpgaintf ${fpgaintf_handoff}; " "go $fpga2sdram_apply; " "mw $fpga2sdram ${fpga2sdram_handoff}; " "mw $axibridge ${axibridge_handoff}; " "mw $l3remap ${l3remap_handoff} "); setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); /* * Relocate the sdram_applycfg_ocram function to OCRAM and call it */ ENTRY(sdram_applycfg_uboot) PUSH {r4-r11, lr} /* save registers per AAPCS */ ldr r1, =sdram_applycfg_ocram ldr r2, =CONFIG_SYS_INIT_RAM_ADDR mov r3, r2 ldmia r1!, {r4 - r11} stmia r3!, {r4 - r11} ldmia r1!, {r4 - r11} /* copy more in case code added */ stmia r3!, {r4 - r11} /* in the future */ ldmia r1!, {r4 - r11} /* copy more in case code added */ stmia r3!, {r4 - r11} /* in the future */ dsb isb blx r2 /* jump to OCRAM */ POP {r4-r11, pc} ENDPROC(sdram_applycfg_uboot) it could be an option to write the fpga firmware with u-boot, and do a soft reset. boot u-boot check fpga configuration state not configured write firmware reset if configured boot linux i ll check howto to determine the fpga configuration state and try this. Thanks
On Thu, Feb 6, 2020 at 3:41 PM Nico Becker <n.becker at ic-automation.de> wrote: > > Am 06.02.2020 um 14:00 schrieb Marek Vasut: > > On 2/6/20 1:57 PM, Nico Becker wrote: > >> Am 06.02.2020 um 12:53 schrieb Marek Vasut: > >>> On 2/6/20 11:50 AM, Nico Becker wrote: > >>>> Hello, > >>> > >>> Hi, > >>> > >>>> after removing the function socfpga_sdram_apply_static_cfg() in > >>>> misc_gen5 we can not use the FPGA2SDRAM bridge. > >>>> > >>>> Without the apply static cfg the kernel crash every time, > >>>> if we try to write @ the fpga2sdram bridge. After an soft reset > >>>> everything is working. > >>>> > >>>> If we add the socfpga_sdram_apply_static_cfg() in the > >>>> u-boot source code, everything is fine. > >>>> Now we can use the fpga2sdram bridge after power on. > >>>> > >>>> Our setup: > >>>> - u-boot v2020.01 > >>>> - load and write fpga firmware > >>>> - enable bridges > >>>> - boot linux > >>>> > >>>> I have found some information at > >>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> > >>>> > >>>> > >>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> > >>> > >>> Can you send a patch which fixes this for you, with Fixes: tag ? > >>> Then it would be clear what you changed. > >>> > >>> Thanks > >>> > >> > >> Hello, > >> the code was removed @ commit c5f4b805. > > > > Did you read the commit message of that commit and what problem that was > > solving ? Clearly, reverting the commit isn't the way to go. We need to > > find a way to unbreak this for you, while not break other platforms. > > > >> I attached my patch, sorry for the format, i am new in this. > > > > [...] > > > Hi, > yes i read the commit message. > > but i found no other option to enable the sdram bridges, > without crashes/hanging up linux, with the removed source code. > > i ve found some more information @intel > <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> > > Intel talk about an bridge_enable_handoff in my opionion > the cmd set the sram aply cfg > > /* add signle command to enable all bridges based on handoff */ > setenv("bridge_enable_handoff", > "mw $fpgaintf ${fpgaintf_handoff}; " > "go $fpga2sdram_apply; " > "mw $fpga2sdram ${fpga2sdram_handoff}; " > "mw $axibridge ${axibridge_handoff}; " > "mw $l3remap ${l3remap_handoff} "); > > setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); > > /* > * Relocate the sdram_applycfg_ocram function to OCRAM and call it > */ > ENTRY(sdram_applycfg_uboot) > PUSH {r4-r11, lr} /* save registers per AAPCS */ > > ldr r1, =sdram_applycfg_ocram > ldr r2, =CONFIG_SYS_INIT_RAM_ADDR > mov r3, r2 > ldmia r1!, {r4 - r11} > stmia r3!, {r4 - r11} > ldmia r1!, {r4 - r11} /* copy more in case code added */ > stmia r3!, {r4 - r11} /* in the future */ > ldmia r1!, {r4 - r11} /* copy more in case code added */ > stmia r3!, {r4 - r11} /* in the future */ > dsb > isb > blx r2 /* jump to OCRAM */ > POP {r4-r11, pc} > ENDPROC(sdram_applycfg_uboot) > > > it could be an option to write the fpga firmware with u-boot, > and do a soft reset. > boot u-boot > check fpga configuration state > not configured write firmware reset > if configured boot linux > > i ll check howto to determine the fpga configuration state > and try this. That doesn't look like a safe plan: what if you explicitly *want* a reboot and want to reconfigure the FPGA then to ensure it is in a well-known state? Marek, what were the problems why this has been removed? Aside from "is confirmed to lead to a rare system hang when enabling bridges", the commit message stays rather vague. Maybe that "apply config" bit should only be written if explicitly configured so, but that would mean we need some kind of config options included/coming with the FPGA image we program. Oh, and by now I'm glad our own design connects to DDR via the main bus ;-) Regards, Simon
On 2/6/20 3:57 PM, Simon Goldschmidt wrote: > On Thu, Feb 6, 2020 at 3:41 PM Nico Becker <n.becker at ic-automation.de> wrote: >> >> Am 06.02.2020 um 14:00 schrieb Marek Vasut: >>> On 2/6/20 1:57 PM, Nico Becker wrote: >>>> Am 06.02.2020 um 12:53 schrieb Marek Vasut: >>>>> On 2/6/20 11:50 AM, Nico Becker wrote: >>>>>> Hello, >>>>> >>>>> Hi, >>>>> >>>>>> after removing the function socfpga_sdram_apply_static_cfg() in >>>>>> misc_gen5 we can not use the FPGA2SDRAM bridge. >>>>>> >>>>>> Without the apply static cfg the kernel crash every time, >>>>>> if we try to write @ the fpga2sdram bridge. After an soft reset >>>>>> everything is working. >>>>>> >>>>>> If we add the socfpga_sdram_apply_static_cfg() in the >>>>>> u-boot source code, everything is fine. >>>>>> Now we can use the fpga2sdram bridge after power on. >>>>>> >>>>>> Our setup: >>>>>> - u-boot v2020.01 >>>>>> - load and write fpga firmware >>>>>> - enable bridges >>>>>> - boot linux >>>>>> >>>>>> I have found some information at >>>>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> >>>>>> >>>>>> >>>>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> >>>>> >>>>> Can you send a patch which fixes this for you, with Fixes: tag ? >>>>> Then it would be clear what you changed. >>>>> >>>>> Thanks >>>>> >>>> >>>> Hello, >>>> the code was removed @ commit c5f4b805. >>> >>> Did you read the commit message of that commit and what problem that was >>> solving ? Clearly, reverting the commit isn't the way to go. We need to >>> find a way to unbreak this for you, while not break other platforms. >>> >>>> I attached my patch, sorry for the format, i am new in this. >>> >>> [...] >>> >> Hi, >> yes i read the commit message. >> >> but i found no other option to enable the sdram bridges, >> without crashes/hanging up linux, with the removed source code. >> >> i ve found some more information @intel >> <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> >> >> Intel talk about an bridge_enable_handoff in my opionion >> the cmd set the sram aply cfg >> >> /* add signle command to enable all bridges based on handoff */ >> setenv("bridge_enable_handoff", >> "mw $fpgaintf ${fpgaintf_handoff}; " >> "go $fpga2sdram_apply; " >> "mw $fpga2sdram ${fpga2sdram_handoff}; " >> "mw $axibridge ${axibridge_handoff}; " >> "mw $l3remap ${l3remap_handoff} "); >> >> setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); >> >> /* >> * Relocate the sdram_applycfg_ocram function to OCRAM and call it >> */ >> ENTRY(sdram_applycfg_uboot) >> PUSH {r4-r11, lr} /* save registers per AAPCS */ >> >> ldr r1, =sdram_applycfg_ocram >> ldr r2, =CONFIG_SYS_INIT_RAM_ADDR >> mov r3, r2 >> ldmia r1!, {r4 - r11} >> stmia r3!, {r4 - r11} >> ldmia r1!, {r4 - r11} /* copy more in case code added */ >> stmia r3!, {r4 - r11} /* in the future */ >> ldmia r1!, {r4 - r11} /* copy more in case code added */ >> stmia r3!, {r4 - r11} /* in the future */ >> dsb >> isb >> blx r2 /* jump to OCRAM */ >> POP {r4-r11, pc} >> ENDPROC(sdram_applycfg_uboot) >> >> >> it could be an option to write the fpga firmware with u-boot, >> and do a soft reset. >> boot u-boot >> check fpga configuration state >> not configured write firmware reset >> if configured boot linux >> >> i ll check howto to determine the fpga configuration state >> and try this. > > That doesn't look like a safe plan: what if you explicitly *want* a reboot > and want to reconfigure the FPGA then to ensure it is in a well-known state? > > Marek, what were the problems why this has been removed? Aside from "is > confirmed to lead to a rare system hang when enabling bridges", the commit > message stays rather vague. That's exactly what the problem was. I didn't manage to get further details from Altera on this. > Maybe that "apply config" bit should only be written > if explicitly configured so, but that would mean we need some kind of config > options included/coming with the FPGA image we program. Maybe the apply config should only be used if the F2S bridge is being used ? > Oh, and by now I'm glad our own design connects to DDR via the main bus ;-) Right.
On Fri, Feb 7, 2020 at 8:56 AM Marek Vasut <marex at denx.de> wrote: > > On 2/6/20 3:57 PM, Simon Goldschmidt wrote: > > On Thu, Feb 6, 2020 at 3:41 PM Nico Becker <n.becker at ic-automation.de> wrote: > >> > >> Am 06.02.2020 um 14:00 schrieb Marek Vasut: > >>> On 2/6/20 1:57 PM, Nico Becker wrote: > >>>> Am 06.02.2020 um 12:53 schrieb Marek Vasut: > >>>>> On 2/6/20 11:50 AM, Nico Becker wrote: > >>>>>> Hello, > >>>>> > >>>>> Hi, > >>>>> > >>>>>> after removing the function socfpga_sdram_apply_static_cfg() in > >>>>>> misc_gen5 we can not use the FPGA2SDRAM bridge. > >>>>>> > >>>>>> Without the apply static cfg the kernel crash every time, > >>>>>> if we try to write @ the fpga2sdram bridge. After an soft reset > >>>>>> everything is working. > >>>>>> > >>>>>> If we add the socfpga_sdram_apply_static_cfg() in the > >>>>>> u-boot source code, everything is fine. > >>>>>> Now we can use the fpga2sdram bridge after power on. > >>>>>> > >>>>>> Our setup: > >>>>>> - u-boot v2020.01 > >>>>>> - load and write fpga firmware > >>>>>> - enable bridges > >>>>>> - boot linux > >>>>>> > >>>>>> I have found some information at > >>>>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> > >>>>>> > >>>>>> > >>>>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> > >>>>> > >>>>> Can you send a patch which fixes this for you, with Fixes: tag ? > >>>>> Then it would be clear what you changed. > >>>>> > >>>>> Thanks > >>>>> > >>>> > >>>> Hello, > >>>> the code was removed @ commit c5f4b805. > >>> > >>> Did you read the commit message of that commit and what problem that was > >>> solving ? Clearly, reverting the commit isn't the way to go. We need to > >>> find a way to unbreak this for you, while not break other platforms. > >>> > >>>> I attached my patch, sorry for the format, i am new in this. > >>> > >>> [...] > >>> > >> Hi, > >> yes i read the commit message. > >> > >> but i found no other option to enable the sdram bridges, > >> without crashes/hanging up linux, with the removed source code. > >> > >> i ve found some more information @intel > >> <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> > >> > >> Intel talk about an bridge_enable_handoff in my opionion > >> the cmd set the sram aply cfg > >> > >> /* add signle command to enable all bridges based on handoff */ > >> setenv("bridge_enable_handoff", > >> "mw $fpgaintf ${fpgaintf_handoff}; " > >> "go $fpga2sdram_apply; " > >> "mw $fpga2sdram ${fpga2sdram_handoff}; " > >> "mw $axibridge ${axibridge_handoff}; " > >> "mw $l3remap ${l3remap_handoff} "); > >> > >> setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); > >> > >> /* > >> * Relocate the sdram_applycfg_ocram function to OCRAM and call it > >> */ > >> ENTRY(sdram_applycfg_uboot) > >> PUSH {r4-r11, lr} /* save registers per AAPCS */ > >> > >> ldr r1, =sdram_applycfg_ocram > >> ldr r2, =CONFIG_SYS_INIT_RAM_ADDR > >> mov r3, r2 > >> ldmia r1!, {r4 - r11} > >> stmia r3!, {r4 - r11} > >> ldmia r1!, {r4 - r11} /* copy more in case code added */ > >> stmia r3!, {r4 - r11} /* in the future */ > >> ldmia r1!, {r4 - r11} /* copy more in case code added */ > >> stmia r3!, {r4 - r11} /* in the future */ > >> dsb > >> isb > >> blx r2 /* jump to OCRAM */ > >> POP {r4-r11, pc} > >> ENDPROC(sdram_applycfg_uboot) > >> > >> > >> it could be an option to write the fpga firmware with u-boot, > >> and do a soft reset. > >> boot u-boot > >> check fpga configuration state > >> not configured write firmware reset > >> if configured boot linux > >> > >> i ll check howto to determine the fpga configuration state > >> and try this. > > > > That doesn't look like a safe plan: what if you explicitly *want* a reboot > > and want to reconfigure the FPGA then to ensure it is in a well-known state? > > > > Marek, what were the problems why this has been removed? Aside from "is > > confirmed to lead to a rare system hang when enabling bridges", the commit > > message stays rather vague. > > That's exactly what the problem was. I didn't manage to get further > details from Altera on this. Hrmpf :-( > > > Maybe that "apply config" bit should only be written > > if explicitly configured so, but that would mean we need some kind of config > > options included/coming with the FPGA image we program. > > Maybe the apply config should only be used if the F2S bridge is being used ? Yes, well how do you know after programming an FPGA that this bridge is in use? This depends on the FPGA image, while currently the Altera work flow compiles it into the U-Boot binary.While I'm still working on moving this into the U-Boot dts (I still have size issues there), it's still not encoded with the FPGA. What we would need is some kind of meta info with the FPGA image that tells us how to configure the bridges (and maybe some clocks or hardware handed off into the FPGA) after programming the FPGA. Only then, we could write the apply config bit after programming the FPGA. As to the "SDRAM access must be idle", I think that should work from U-Boot. All peripherals should be idle, unless the FPGA accesses SDRAM right after being configured. Maybe we'd need to wait a bit in case the cache is filling a line or so... Regards, Simon > > > Oh, and by now I'm glad our own design connects to DDR via the main bus ;-) > > Right. > > -- > Best regards, > Marek Vasut
On 2/7/20 1:09 PM, Simon Goldschmidt wrote: > On Fri, Feb 7, 2020 at 8:56 AM Marek Vasut <marex at denx.de> wrote: >> >> On 2/6/20 3:57 PM, Simon Goldschmidt wrote: >>> On Thu, Feb 6, 2020 at 3:41 PM Nico Becker <n.becker at ic-automation.de> wrote: >>>> >>>> Am 06.02.2020 um 14:00 schrieb Marek Vasut: >>>>> On 2/6/20 1:57 PM, Nico Becker wrote: >>>>>> Am 06.02.2020 um 12:53 schrieb Marek Vasut: >>>>>>> On 2/6/20 11:50 AM, Nico Becker wrote: >>>>>>>> Hello, >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>>> after removing the function socfpga_sdram_apply_static_cfg() in >>>>>>>> misc_gen5 we can not use the FPGA2SDRAM bridge. >>>>>>>> >>>>>>>> Without the apply static cfg the kernel crash every time, >>>>>>>> if we try to write @ the fpga2sdram bridge. After an soft reset >>>>>>>> everything is working. >>>>>>>> >>>>>>>> If we add the socfpga_sdram_apply_static_cfg() in the >>>>>>>> u-boot source code, everything is fine. >>>>>>>> Now we can use the fpga2sdram bridge after power on. >>>>>>>> >>>>>>>> Our setup: >>>>>>>> - u-boot v2020.01 >>>>>>>> - load and write fpga firmware >>>>>>>> - enable bridges >>>>>>>> - boot linux >>>>>>>> >>>>>>>> I have found some information at >>>>>>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> >>>>>>>> >>>>>>>> >>>>>>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> >>>>>>> >>>>>>> Can you send a patch which fixes this for you, with Fixes: tag ? >>>>>>> Then it would be clear what you changed. >>>>>>> >>>>>>> Thanks >>>>>>> >>>>>> >>>>>> Hello, >>>>>> the code was removed @ commit c5f4b805. >>>>> >>>>> Did you read the commit message of that commit and what problem that was >>>>> solving ? Clearly, reverting the commit isn't the way to go. We need to >>>>> find a way to unbreak this for you, while not break other platforms. >>>>> >>>>>> I attached my patch, sorry for the format, i am new in this. >>>>> >>>>> [...] >>>>> >>>> Hi, >>>> yes i read the commit message. >>>> >>>> but i found no other option to enable the sdram bridges, >>>> without crashes/hanging up linux, with the removed source code. >>>> >>>> i ve found some more information @intel >>>> <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> >>>> >>>> Intel talk about an bridge_enable_handoff in my opionion >>>> the cmd set the sram aply cfg >>>> >>>> /* add signle command to enable all bridges based on handoff */ >>>> setenv("bridge_enable_handoff", >>>> "mw $fpgaintf ${fpgaintf_handoff}; " >>>> "go $fpga2sdram_apply; " >>>> "mw $fpga2sdram ${fpga2sdram_handoff}; " >>>> "mw $axibridge ${axibridge_handoff}; " >>>> "mw $l3remap ${l3remap_handoff} "); >>>> >>>> setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); >>>> >>>> /* >>>> * Relocate the sdram_applycfg_ocram function to OCRAM and call it >>>> */ >>>> ENTRY(sdram_applycfg_uboot) >>>> PUSH {r4-r11, lr} /* save registers per AAPCS */ >>>> >>>> ldr r1, =sdram_applycfg_ocram >>>> ldr r2, =CONFIG_SYS_INIT_RAM_ADDR >>>> mov r3, r2 >>>> ldmia r1!, {r4 - r11} >>>> stmia r3!, {r4 - r11} >>>> ldmia r1!, {r4 - r11} /* copy more in case code added */ >>>> stmia r3!, {r4 - r11} /* in the future */ >>>> ldmia r1!, {r4 - r11} /* copy more in case code added */ >>>> stmia r3!, {r4 - r11} /* in the future */ >>>> dsb >>>> isb >>>> blx r2 /* jump to OCRAM */ >>>> POP {r4-r11, pc} >>>> ENDPROC(sdram_applycfg_uboot) >>>> >>>> >>>> it could be an option to write the fpga firmware with u-boot, >>>> and do a soft reset. >>>> boot u-boot >>>> check fpga configuration state >>>> not configured write firmware reset >>>> if configured boot linux >>>> >>>> i ll check howto to determine the fpga configuration state >>>> and try this. >>> >>> That doesn't look like a safe plan: what if you explicitly *want* a reboot >>> and want to reconfigure the FPGA then to ensure it is in a well-known state? >>> >>> Marek, what were the problems why this has been removed? Aside from "is >>> confirmed to lead to a rare system hang when enabling bridges", the commit >>> message stays rather vague. >> >> That's exactly what the problem was. I didn't manage to get further >> details from Altera on this. > > Hrmpf :-( > >> >>> Maybe that "apply config" bit should only be written >>> if explicitly configured so, but that would mean we need some kind of config >>> options included/coming with the FPGA image we program. >> >> Maybe the apply config should only be used if the F2S bridge is being used ? > > Yes, well how do you know after programming an FPGA that this bridge is in use? >From the handoff files ? > This depends on the FPGA image, while currently the Altera work flow compiles > it into the U-Boot binary.While I'm still working on moving this into the U-Boot > dts (I still have size issues there), it's still not encoded with the FPGA. Well you can dig this information out of the handoff files , so you can also make this somehow configurable via either DT or bridge command args. > What we would need is some kind of meta info with the FPGA image that tells us > how to configure the bridges (and maybe some clocks or hardware handed off into > the FPGA) after programming the FPGA. fitImage ? :) > Only then, we could write the apply config bit after programming the FPGA. > > As to the "SDRAM access must be idle", I think that should work from U-Boot. All > peripherals should be idle, unless the FPGA accesses SDRAM right after being > configured. Maybe we'd need to wait a bit in case the cache is filling a line > or so... ... or something is queued up in some buffer somewhere in the bridge.
On Fri, Feb 7, 2020 at 1:27 PM Marek Vasut <marex at denx.de> wrote: > > On 2/7/20 1:09 PM, Simon Goldschmidt wrote: > > On Fri, Feb 7, 2020 at 8:56 AM Marek Vasut <marex at denx.de> wrote: > >> > >> On 2/6/20 3:57 PM, Simon Goldschmidt wrote: > >>> On Thu, Feb 6, 2020 at 3:41 PM Nico Becker <n.becker at ic-automation.de> wrote: > >>>> > >>>> Am 06.02.2020 um 14:00 schrieb Marek Vasut: > >>>>> On 2/6/20 1:57 PM, Nico Becker wrote: > >>>>>> Am 06.02.2020 um 12:53 schrieb Marek Vasut: > >>>>>>> On 2/6/20 11:50 AM, Nico Becker wrote: > >>>>>>>> Hello, > >>>>>>> > >>>>>>> Hi, > >>>>>>> > >>>>>>>> after removing the function socfpga_sdram_apply_static_cfg() in > >>>>>>>> misc_gen5 we can not use the FPGA2SDRAM bridge. > >>>>>>>> > >>>>>>>> Without the apply static cfg the kernel crash every time, > >>>>>>>> if we try to write @ the fpga2sdram bridge. After an soft reset > >>>>>>>> everything is working. > >>>>>>>> > >>>>>>>> If we add the socfpga_sdram_apply_static_cfg() in the > >>>>>>>> u-boot source code, everything is fine. > >>>>>>>> Now we can use the fpga2sdram bridge after power on. > >>>>>>>> > >>>>>>>> Our setup: > >>>>>>>> - u-boot v2020.01 > >>>>>>>> - load and write fpga firmware > >>>>>>>> - enable bridges > >>>>>>>> - boot linux > >>>>>>>> > >>>>>>>> I have found some information at > >>>>>>>> <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge> > >>>>>>>> > >>>>>>>> > >>>>>>>> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> > >>>>>>> > >>>>>>> Can you send a patch which fixes this for you, with Fixes: tag ? > >>>>>>> Then it would be clear what you changed. > >>>>>>> > >>>>>>> Thanks > >>>>>>> > >>>>>> > >>>>>> Hello, > >>>>>> the code was removed @ commit c5f4b805. > >>>>> > >>>>> Did you read the commit message of that commit and what problem that was > >>>>> solving ? Clearly, reverting the commit isn't the way to go. We need to > >>>>> find a way to unbreak this for you, while not break other platforms. > >>>>> > >>>>>> I attached my patch, sorry for the format, i am new in this. > >>>>> > >>>>> [...] > >>>>> > >>>> Hi, > >>>> yes i read the commit message. > >>>> > >>>> but i found no other option to enable the sdram bridges, > >>>> without crashes/hanging up linux, with the removed source code. > >>>> > >>>> i ve found some more information @intel > >>>> <https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html> > >>>> > >>>> Intel talk about an bridge_enable_handoff in my opionion > >>>> the cmd set the sram aply cfg > >>>> > >>>> /* add signle command to enable all bridges based on handoff */ > >>>> setenv("bridge_enable_handoff", > >>>> "mw $fpgaintf ${fpgaintf_handoff}; " > >>>> "go $fpga2sdram_apply; " > >>>> "mw $fpga2sdram ${fpga2sdram_handoff}; " > >>>> "mw $axibridge ${axibridge_handoff}; " > >>>> "mw $l3remap ${l3remap_handoff} "); > >>>> > >>>> setenv_addr("fpga2sdram_apply", (void *)sdram_applycfg_uboot); > >>>> > >>>> /* > >>>> * Relocate the sdram_applycfg_ocram function to OCRAM and call it > >>>> */ > >>>> ENTRY(sdram_applycfg_uboot) > >>>> PUSH {r4-r11, lr} /* save registers per AAPCS */ > >>>> > >>>> ldr r1, =sdram_applycfg_ocram > >>>> ldr r2, =CONFIG_SYS_INIT_RAM_ADDR > >>>> mov r3, r2 > >>>> ldmia r1!, {r4 - r11} > >>>> stmia r3!, {r4 - r11} > >>>> ldmia r1!, {r4 - r11} /* copy more in case code added */ > >>>> stmia r3!, {r4 - r11} /* in the future */ > >>>> ldmia r1!, {r4 - r11} /* copy more in case code added */ > >>>> stmia r3!, {r4 - r11} /* in the future */ > >>>> dsb > >>>> isb > >>>> blx r2 /* jump to OCRAM */ > >>>> POP {r4-r11, pc} > >>>> ENDPROC(sdram_applycfg_uboot) > >>>> > >>>> > >>>> it could be an option to write the fpga firmware with u-boot, > >>>> and do a soft reset. > >>>> boot u-boot > >>>> check fpga configuration state > >>>> not configured write firmware reset > >>>> if configured boot linux > >>>> > >>>> i ll check howto to determine the fpga configuration state > >>>> and try this. > >>> > >>> That doesn't look like a safe plan: what if you explicitly *want* a reboot > >>> and want to reconfigure the FPGA then to ensure it is in a well-known state? > >>> > >>> Marek, what were the problems why this has been removed? Aside from "is > >>> confirmed to lead to a rare system hang when enabling bridges", the commit > >>> message stays rather vague. > >> > >> That's exactly what the problem was. I didn't manage to get further > >> details from Altera on this. > > > > Hrmpf :-( > > > >> > >>> Maybe that "apply config" bit should only be written > >>> if explicitly configured so, but that would mean we need some kind of config > >>> options included/coming with the FPGA image we program. > >> > >> Maybe the apply config should only be used if the F2S bridge is being used ? > > > > Yes, well how do you know after programming an FPGA that this bridge is in use? > > From the handoff files ? Yeah, well, I know that. I meant this is not available in U-Boot, see below. > > > This depends on the FPGA image, while currently the Altera work flow compiles > > it into the U-Boot binary.While I'm still working on moving this into the U-Boot > > dts (I still have size issues there), it's still not encoded with the FPGA. > > Well you can dig this information out of the handoff files , so you can > also make this somehow configurable via either DT or bridge command args. My point was this can differ between FPGA images. Once you load an FPGA image that doesn't match what you expected when building (or flashing) U-Boot, the system may lock up again. DT is not an option, as you hard-code it when flashing U-Boot. The loaded FPGA image can still change.Bridge command args is a way of how to get this info into the code that runs, but from where do these command args come? You need to somehow parse this info from an FPGA image file read from storage. > > > What we would need is some kind of meta info with the FPGA image that tells us > > how to configure the bridges (and maybe some clocks or hardware handed off into > > the FPGA) after programming the FPGA. > > fitImage ? :) I thought of that, too. Maybe a short dts (maybe overlay) beside the FPGA. But then it would again not work when loading a pure rbf. But then again, that might be ok... So I could imagine this to "just work" when someday I finally have finished my series of moving this handoff info into dts and then including an overlay dts into a fit image that gets applied after programming the FPGA (and by/after applying it, the code that applies bridge settings would run). Would that work? Regards, Simon > > > Only then, we could write the apply config bit after programming the FPGA. > > > > As to the "SDRAM access must be idle", I think that should work from U-Boot. All > > peripherals should be idle, unless the FPGA accesses SDRAM right after being > > configured. Maybe we'd need to wait a bit in case the cache is filling a line > > or so... > > ... or something is queued up in some buffer somewhere in the bridge.
On 2/7/20 2:44 PM, Simon Goldschmidt wrote: [...] >>> This depends on the FPGA image, while currently the Altera work flow compiles >>> it into the U-Boot binary.While I'm still working on moving this into the U-Boot >>> dts (I still have size issues there), it's still not encoded with the FPGA. >> >> Well you can dig this information out of the handoff files , so you can >> also make this somehow configurable via either DT or bridge command args. > > > My point was this can differ between FPGA images. Once you load an FPGA image > that doesn't match what you expected when building (or flashing) U-Boot, the > system may lock up again. > > DT is not an option, as you hard-code it when flashing U-Boot. You can apply a DTO on the U-Boot DT :-) > The loaded FPGA > image can still change.Bridge command args is a way of how to get this info into > the code that runs, but from where do these command args come? You need to > somehow parse this info from an FPGA image file read from storage. Maybe this could be part of a fitImage or DTO bundled with the FPGA image ? >>> What we would need is some kind of meta info with the FPGA image that tells us >>> how to configure the bridges (and maybe some clocks or hardware handed off into >>> the FPGA) after programming the FPGA. >> >> fitImage ? :) > I thought of that, too. Maybe a short dts (maybe overlay) beside the FPGA. But > then it would again not work when loading a pure rbf. But then again, that might > be ok... That's probably OK. If you're loading pure RBF, then you know what you're doing. > So I could imagine this to "just work" when someday I finally have finished my > series of moving this handoff info into dts and then including an overlay dts > into a fit image that gets applied after programming the FPGA (and by/after > applying it, the code that applies bridge settings would run). Would that work? I think so.
I am reading through this thread, and want to point out that it is not that the FPGA bridge need be actively used in the fpga, but rather that this port be configured in the FPGA configuration. This is an important distinction, ecery FPGA design that instantiates the HPS does configure the F2S Bridge. it drives select pins, control pins, data pins, etc, on the interface to known values, and so the apply can always be done as all SoC FPGA designs have the soc instantiated. If someone boots the arm, and uses an FPGA design without having the soc instantiated, it may then cause issues, but i would argue that is not a supported use in the first place. --dalon On Fri, 2020-02-07 at 14:49 +0100, Marek Vasut wrote: > On 2/7/20 2:44 PM, Simon Goldschmidt wrote: > > [...] > > > > > This depends on the FPGA image, while currently the Altera work flow compiles > > > > it into the U-Boot binary.While I'm still working on moving this into the U-Boot > > > > dts (I still have size issues there), it's still not encoded with the FPGA. > > > > > > Well you can dig this information out of the handoff files , so you can > > > also make this somehow configurable via either DT or bridge command args. > > > > > > My point was this can differ between FPGA images. Once you load an FPGA image > > that doesn't match what you expected when building (or flashing) U-Boot, the > > system may lock up again. > > > > DT is not an option, as you hard-code it when flashing U-Boot. > > You can apply a DTO on the U-Boot DT :-) > > > The loaded FPGA > > image can still change.Bridge command args is a way of how to get this info into > > the code that runs, but from where do these command args come? You need to > > somehow parse this info from an FPGA image file read from storage. > > Maybe this could be part of a fitImage or DTO bundled with the FPGA image ? > > > > > What we would need is some kind of meta info with the FPGA image that tells us > > > > how to configure the bridges (and maybe some clocks or hardware handed off into > > > > the FPGA) after programming the FPGA. > > > > > > fitImage ? :) > > I thought of that, too. Maybe a short dts (maybe overlay) beside the FPGA. But > > then it would again not work when loading a pure rbf. But then again, that might > > be ok... > > That's probably OK. If you're loading pure RBF, then you know what > you're doing. > > > So I could imagine this to "just work" when someday I finally have finished my > > series of moving this handoff info into dts and then including an overlay dts > > into a fit image that gets applied after programming the FPGA (and by/after > > applying it, the code that applies bridge settings would run). Would that work? > > I think so.
On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen <dalon.westergreen at linux.intel.com> wrote: > > I am reading through this thread, and want to point out that it is not that the > FPGA bridge need be actively used in the fpga, but > rather that this port be configured in the FPGA configuration. This is an > important distinction, ecery FPGA design that > instantiates the HPS does configure the F2S Bridge. it drives select pins, > control pins, data pins, etc, on the interface to known values, > and so the apply can always be done as all SoC FPGA designs have the soc > instantiated. If someone boots the arm, and uses an > FPGA design without having the soc instantiated, it may then cause issues, but i > would argue that is not a supported use > in the first place. > > --dalon > I can reproduce the issue if without setting applycfg bit. Access to F2sdram interface will cause system hang. >From the Cyclone 5 Soc datasheet: applycfg - Write with this bit set to apply all the settings loaded in SDR registers to the memory interface. This bit is write-only and always returns 0 if read. Software should set applycfg bit if change any register under SDR register range. SW is allowed to set this bit multiple times, the only condition is SDRAM need to be idle. My suggestion is we add back socfpga_sdram_apply_static_cfg(), but change the sequence to below: writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); socfpga_sdram_apply_static_cfg(); Marek and Simon, are you okay with this? If yes, I will submit patch for this. Thanks. Regards Ley Foon
On 3/9/20 9:50 AM, Ley Foon Tan wrote: > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > <dalon.westergreen at linux.intel.com> wrote: >> >> I am reading through this thread, and want to point out that it is not that the >> FPGA bridge need be actively used in the fpga, but >> rather that this port be configured in the FPGA configuration. This is an >> important distinction, ecery FPGA design that >> instantiates the HPS does configure the F2S Bridge. it drives select pins, >> control pins, data pins, etc, on the interface to known values, >> and so the apply can always be done as all SoC FPGA designs have the soc >> instantiated. If someone boots the arm, and uses an >> FPGA design without having the soc instantiated, it may then cause issues, but i >> would argue that is not a supported use >> in the first place. >> >> --dalon >> > > I can reproduce the issue if without setting applycfg bit. Access to > F2sdram interface will cause system hang. > > From the Cyclone 5 Soc datasheet: > applycfg - Write with this bit set to apply all the settings loaded in > SDR registers to the memory interface. This bit is write-only and > always returns 0 if read. > > Software should set applycfg bit if change any register under SDR > register range. SW is allowed to set this bit multiple times, the only > condition is SDRAM need to be idle. > My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > change the sequence to below: > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > socfpga_sdram_apply_static_cfg(); > > Marek and Simon, are you okay with this? If yes, I will submit patch for this. The problem was that this was causing weird sporadic hangs on Gen5, which is why it was removed. So until there is an explanation for those hangs, I'm not really OK with this. Maybe the application of static config should happen in SPL, before the DRAM is running, or something like that ?
On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: > > On 3/9/20 9:50 AM, Ley Foon Tan wrote: > > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > > <dalon.westergreen at linux.intel.com> wrote: > >> > >> I am reading through this thread, and want to point out that it is not that the > >> FPGA bridge need be actively used in the fpga, but > >> rather that this port be configured in the FPGA configuration. This is an > >> important distinction, ecery FPGA design that > >> instantiates the HPS does configure the F2S Bridge. it drives select pins, > >> control pins, data pins, etc, on the interface to known values, > >> and so the apply can always be done as all SoC FPGA designs have the soc > >> instantiated. If someone boots the arm, and uses an > >> FPGA design without having the soc instantiated, it may then cause issues, but i > >> would argue that is not a supported use > >> in the first place. > >> > >> --dalon > >> > > > > I can reproduce the issue if without setting applycfg bit. Access to > > F2sdram interface will cause system hang. > > > > From the Cyclone 5 Soc datasheet: > > applycfg - Write with this bit set to apply all the settings loaded in > > SDR registers to the memory interface. This bit is write-only and > > always returns 0 if read. > > > > Software should set applycfg bit if change any register under SDR > > register range. SW is allowed to set this bit multiple times, the only > > condition is SDRAM need to be idle. > > My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > > change the sequence to below: > > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > > socfpga_sdram_apply_static_cfg(); > > > > Marek and Simon, are you okay with this? If yes, I will submit patch for this. > > The problem was that this was causing weird sporadic hangs on Gen5, > which is why it was removed. So until there is an explanation for those > hangs, I'm not really OK with this. These sporadic hangs you saw were on devices without an FPGA image directly accessing the SDRAM ports, right? > > Maybe the application of static config should happen in SPL, before the > DRAM is running, or something like that ? Thinking this further, limiting it to applying in SPL is not a good idea since that prevents us from implementing different FPGA images/configs by loading a config later in the boot (i.e. in U-Boot from a FIT-image). Would it work to make setting this optional, i.e. only write the bit if an FPGA config actually uses these ports? Then it couldn't lead to problems on other hardware... Regards, Simon
On 3/9/20 3:10 PM, Simon Goldschmidt wrote: > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: >> >> On 3/9/20 9:50 AM, Ley Foon Tan wrote: >>> On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen >>> <dalon.westergreen at linux.intel.com> wrote: >>>> >>>> I am reading through this thread, and want to point out that it is not that the >>>> FPGA bridge need be actively used in the fpga, but >>>> rather that this port be configured in the FPGA configuration. This is an >>>> important distinction, ecery FPGA design that >>>> instantiates the HPS does configure the F2S Bridge. it drives select pins, >>>> control pins, data pins, etc, on the interface to known values, >>>> and so the apply can always be done as all SoC FPGA designs have the soc >>>> instantiated. If someone boots the arm, and uses an >>>> FPGA design without having the soc instantiated, it may then cause issues, but i >>>> would argue that is not a supported use >>>> in the first place. >>>> >>>> --dalon >>>> >>> >>> I can reproduce the issue if without setting applycfg bit. Access to >>> F2sdram interface will cause system hang. >>> >>> From the Cyclone 5 Soc datasheet: >>> applycfg - Write with this bit set to apply all the settings loaded in >>> SDR registers to the memory interface. This bit is write-only and >>> always returns 0 if read. >>> >>> Software should set applycfg bit if change any register under SDR >>> register range. SW is allowed to set this bit multiple times, the only >>> condition is SDRAM need to be idle. >>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but >>> change the sequence to below: >>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); >>> socfpga_sdram_apply_static_cfg(); >>> >>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. >> >> The problem was that this was causing weird sporadic hangs on Gen5, >> which is why it was removed. So until there is an explanation for those >> hangs, I'm not really OK with this. > > These sporadic hangs you saw were on devices without an FPGA image directly > accessing the SDRAM ports, right? Yes >> Maybe the application of static config should happen in SPL, before the >> DRAM is running, or something like that ? > > Thinking this further, limiting it to applying in SPL is not a good idea since > that prevents us from implementing different FPGA images/configs by loading a > config later in the boot (i.e. in U-Boot from a FIT-image). Well, but later we have SDRAM running and we cannot make it go idle, can we? > Would it work to make setting this optional, i.e. only write the bit if an FPGA > config actually uses these ports? Then it couldn't lead to problems on other > hardware... Can you make SDRAM bus really idle ?
On Mon, Mar 9, 2020 at 3:15 PM Marek Vasut <marex at denx.de> wrote: > > On 3/9/20 3:10 PM, Simon Goldschmidt wrote: > > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: > >> > >> On 3/9/20 9:50 AM, Ley Foon Tan wrote: > >>> On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > >>> <dalon.westergreen at linux.intel.com> wrote: > >>>> > >>>> I am reading through this thread, and want to point out that it is not that the > >>>> FPGA bridge need be actively used in the fpga, but > >>>> rather that this port be configured in the FPGA configuration. This is an > >>>> important distinction, ecery FPGA design that > >>>> instantiates the HPS does configure the F2S Bridge. it drives select pins, > >>>> control pins, data pins, etc, on the interface to known values, > >>>> and so the apply can always be done as all SoC FPGA designs have the soc > >>>> instantiated. If someone boots the arm, and uses an > >>>> FPGA design without having the soc instantiated, it may then cause issues, but i > >>>> would argue that is not a supported use > >>>> in the first place. > >>>> > >>>> --dalon > >>>> > >>> > >>> I can reproduce the issue if without setting applycfg bit. Access to > >>> F2sdram interface will cause system hang. > >>> > >>> From the Cyclone 5 Soc datasheet: > >>> applycfg - Write with this bit set to apply all the settings loaded in > >>> SDR registers to the memory interface. This bit is write-only and > >>> always returns 0 if read. > >>> > >>> Software should set applycfg bit if change any register under SDR > >>> register range. SW is allowed to set this bit multiple times, the only > >>> condition is SDRAM need to be idle. > >>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > >>> change the sequence to below: > >>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > >>> socfpga_sdram_apply_static_cfg(); > >>> > >>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. > >> > >> The problem was that this was causing weird sporadic hangs on Gen5, > >> which is why it was removed. So until there is an explanation for those > >> hangs, I'm not really OK with this. > > > > These sporadic hangs you saw were on devices without an FPGA image directly > > accessing the SDRAM ports, right? > > Yes > > >> Maybe the application of static config should happen in SPL, before the > >> DRAM is running, or something like that ? > > > > Thinking this further, limiting it to applying in SPL is not a good idea since > > that prevents us from implementing different FPGA images/configs by loading a > > config later in the boot (i.e. in U-Boot from a FIT-image). > > Well, but later we have SDRAM running and we cannot make it go idle, can we? > > > Would it work to make setting this optional, i.e. only write the bit if an FPGA > > config actually uses these ports? Then it couldn't lead to problems on other > > hardware... > > Can you make SDRAM bus really idle ? >From the CPU side, that should work, no? Of course you have to make sure no other peripheraly (including FPGA!) are using the RAM. And if this would be an explicit command, people needing this could experiment with it - and hopefully give better hints as to what's going wrong if we *do* see problems again. Regards, Simon
On 3/9/20 3:24 PM, Simon Goldschmidt wrote: > On Mon, Mar 9, 2020 at 3:15 PM Marek Vasut <marex at denx.de> wrote: >> >> On 3/9/20 3:10 PM, Simon Goldschmidt wrote: >>> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: >>>> >>>> On 3/9/20 9:50 AM, Ley Foon Tan wrote: >>>>> On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen >>>>> <dalon.westergreen at linux.intel.com> wrote: >>>>>> >>>>>> I am reading through this thread, and want to point out that it is not that the >>>>>> FPGA bridge need be actively used in the fpga, but >>>>>> rather that this port be configured in the FPGA configuration. This is an >>>>>> important distinction, ecery FPGA design that >>>>>> instantiates the HPS does configure the F2S Bridge. it drives select pins, >>>>>> control pins, data pins, etc, on the interface to known values, >>>>>> and so the apply can always be done as all SoC FPGA designs have the soc >>>>>> instantiated. If someone boots the arm, and uses an >>>>>> FPGA design without having the soc instantiated, it may then cause issues, but i >>>>>> would argue that is not a supported use >>>>>> in the first place. >>>>>> >>>>>> --dalon >>>>>> >>>>> >>>>> I can reproduce the issue if without setting applycfg bit. Access to >>>>> F2sdram interface will cause system hang. >>>>> >>>>> From the Cyclone 5 Soc datasheet: >>>>> applycfg - Write with this bit set to apply all the settings loaded in >>>>> SDR registers to the memory interface. This bit is write-only and >>>>> always returns 0 if read. >>>>> >>>>> Software should set applycfg bit if change any register under SDR >>>>> register range. SW is allowed to set this bit multiple times, the only >>>>> condition is SDRAM need to be idle. >>>>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but >>>>> change the sequence to below: >>>>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); >>>>> socfpga_sdram_apply_static_cfg(); >>>>> >>>>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. >>>> >>>> The problem was that this was causing weird sporadic hangs on Gen5, >>>> which is why it was removed. So until there is an explanation for those >>>> hangs, I'm not really OK with this. >>> >>> These sporadic hangs you saw were on devices without an FPGA image directly >>> accessing the SDRAM ports, right? >> >> Yes >> >>>> Maybe the application of static config should happen in SPL, before the >>>> DRAM is running, or something like that ? >>> >>> Thinking this further, limiting it to applying in SPL is not a good idea since >>> that prevents us from implementing different FPGA images/configs by loading a >>> config later in the boot (i.e. in U-Boot from a FIT-image). >> >> Well, but later we have SDRAM running and we cannot make it go idle, can we? >> >>> Would it work to make setting this optional, i.e. only write the bit if an FPGA >>> config actually uses these ports? Then it couldn't lead to problems on other >>> hardware... >> >> Can you make SDRAM bus really idle ? > > From the CPU side, that should work, no? Of course you have to make sure no > other peripheraly (including FPGA!) are using the RAM. > > And if this would be an explicit command, people needing this could > experiment with it - and hopefully give better hints as to what's going wrong > if we *do* see problems again. Maybe altera has something hidden somewhere in the bus tunables ? :)
On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com> wrote: > > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: > > > > >> > > > > > > I can reproduce the issue if without setting applycfg bit. Access to > > > F2sdram interface will cause system hang. > > > > > > From the Cyclone 5 Soc datasheet: > > > applycfg - Write with this bit set to apply all the settings loaded in > > > SDR registers to the memory interface. This bit is write-only and > > > always returns 0 if read. > > > > > > Software should set applycfg bit if change any register under SDR > > > register range. SW is allowed to set this bit multiple times, the only > > > condition is SDRAM need to be idle. > > > My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > > > change the sequence to below: > > > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > > > socfpga_sdram_apply_static_cfg(); > > > > > > Marek and Simon, are you okay with this? If yes, I will submit patch for this. > > > > The problem was that this was causing weird sporadic hangs on Gen5, > > which is why it was removed. So until there is an explanation for those > > hangs, I'm not really OK with this. > > These sporadic hangs you saw were on devices without an FPGA image directly > accessing the SDRAM ports, right? > > > > > Maybe the application of static config should happen in SPL, before the > > DRAM is running, or something like that ? > > Thinking this further, limiting it to applying in SPL is not a good idea since > that prevents us from implementing different FPGA images/configs by loading a > config later in the boot (i.e. in U-Boot from a FIT-image). > > Would it work to make setting this optional, i.e. only write the bit if an FPGA > config actually uses these ports? Then it couldn't lead to problems on other > hardware... If the sporadic hangs issue happen on FPGA image that doesn't connect to f2sdram interface, we can add the checking to only apply static cfg when it has f2sdram port enabled. It can send a patch with this checking for you to try if want. Regards Ley Foon
On 3/11/20 10:54 AM, Ley Foon Tan wrote: > On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt > <simon.k.r.goldschmidt at gmail.com> wrote: >> >> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: >>> > >>>>> >>>> >>>> I can reproduce the issue if without setting applycfg bit. Access to >>>> F2sdram interface will cause system hang. >>>> >>>> From the Cyclone 5 Soc datasheet: >>>> applycfg - Write with this bit set to apply all the settings loaded in >>>> SDR registers to the memory interface. This bit is write-only and >>>> always returns 0 if read. >>>> >>>> Software should set applycfg bit if change any register under SDR >>>> register range. SW is allowed to set this bit multiple times, the only >>>> condition is SDRAM need to be idle. >>>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but >>>> change the sequence to below: >>>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); >>>> socfpga_sdram_apply_static_cfg(); >>>> >>>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. >>> >>> The problem was that this was causing weird sporadic hangs on Gen5, >>> which is why it was removed. So until there is an explanation for those >>> hangs, I'm not really OK with this. >> >> These sporadic hangs you saw were on devices without an FPGA image directly >> accessing the SDRAM ports, right? >> >>> >>> Maybe the application of static config should happen in SPL, before the >>> DRAM is running, or something like that ? >> >> Thinking this further, limiting it to applying in SPL is not a good idea since >> that prevents us from implementing different FPGA images/configs by loading a >> config later in the boot (i.e. in U-Boot from a FIT-image). >> >> Would it work to make setting this optional, i.e. only write the bit if an FPGA >> config actually uses these ports? Then it couldn't lead to problems on other >> hardware... > > If the sporadic hangs issue happen on FPGA image that doesn't connect > to f2sdram interface, we can add the checking to only apply static cfg > when it has f2sdram port enabled. > It can send a patch with this checking for you to try if want. Well, what could cause that sporadic hang ? Yes, the hang happens on image which doesn't access the SDRAM IIRC.
On Wed, Mar 11, 2020 at 5:58 PM Marek Vasut <marex at denx.de> wrote: > > On 3/11/20 10:54 AM, Ley Foon Tan wrote: > > On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt > > <simon.k.r.goldschmidt at gmail.com> wrote: > >> > >> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: > >>> > > > >>>>> > >>>> > >>>> I can reproduce the issue if without setting applycfg bit. Access to > >>>> F2sdram interface will cause system hang. > >>>> > >>>> From the Cyclone 5 Soc datasheet: > >>>> applycfg - Write with this bit set to apply all the settings loaded in > >>>> SDR registers to the memory interface. This bit is write-only and > >>>> always returns 0 if read. > >>>> > >>>> Software should set applycfg bit if change any register under SDR > >>>> register range. SW is allowed to set this bit multiple times, the only > >>>> condition is SDRAM need to be idle. > >>>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > >>>> change the sequence to below: > >>>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > >>>> socfpga_sdram_apply_static_cfg(); > >>>> > >>>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. > >>> > >>> The problem was that this was causing weird sporadic hangs on Gen5, > >>> which is why it was removed. So until there is an explanation for those > >>> hangs, I'm not really OK with this. > >> > >> These sporadic hangs you saw were on devices without an FPGA image directly > >> accessing the SDRAM ports, right? > >> > >>> > >>> Maybe the application of static config should happen in SPL, before the > >>> DRAM is running, or something like that ? > >> > >> Thinking this further, limiting it to applying in SPL is not a good idea since > >> that prevents us from implementing different FPGA images/configs by loading a > >> config later in the boot (i.e. in U-Boot from a FIT-image). > >> > >> Would it work to make setting this optional, i.e. only write the bit if an FPGA > >> config actually uses these ports? Then it couldn't lead to problems on other > >> hardware... > > > > If the sporadic hangs issue happen on FPGA image that doesn't connect > > to f2sdram interface, we can add the checking to only apply static cfg > > when it has f2sdram port enabled. > > It can send a patch with this checking for you to try if want. > Well, what could cause that sporadic hang ? > Yes, the hang happens on image which doesn't access the SDRAM IIRC. > Do you remember if the hang happen when run bridge enable/disable command? Or other flow? I have tested the following sequence 500 times with FPGA image that doesn't contains fs2dram bridge, but didn't see the hang. - program fpga image - bridge enable - write to h2f bridge - read from h2f bridge - bridge disable - repeat step 1 Regards Ley Foon
On 3/12/20 10:31 AM, Ley Foon Tan wrote: > On Wed, Mar 11, 2020 at 5:58 PM Marek Vasut <marex at denx.de> wrote: >> >> On 3/11/20 10:54 AM, Ley Foon Tan wrote: >>> On Mon, Mar 9, 2020 at 10:10 PM Simon Goldschmidt >>> <simon.k.r.goldschmidt at gmail.com> wrote: >>>> >>>> On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: >>>>> >>> >>>>>>> >>>>>> >>>>>> I can reproduce the issue if without setting applycfg bit. Access to >>>>>> F2sdram interface will cause system hang. >>>>>> >>>>>> From the Cyclone 5 Soc datasheet: >>>>>> applycfg - Write with this bit set to apply all the settings loaded in >>>>>> SDR registers to the memory interface. This bit is write-only and >>>>>> always returns 0 if read. >>>>>> >>>>>> Software should set applycfg bit if change any register under SDR >>>>>> register range. SW is allowed to set this bit multiple times, the only >>>>>> condition is SDRAM need to be idle. >>>>>> My suggestion is we add back socfpga_sdram_apply_static_cfg(), but >>>>>> change the sequence to below: >>>>>> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); >>>>>> socfpga_sdram_apply_static_cfg(); >>>>>> >>>>>> Marek and Simon, are you okay with this? If yes, I will submit patch for this. >>>>> >>>>> The problem was that this was causing weird sporadic hangs on Gen5, >>>>> which is why it was removed. So until there is an explanation for those >>>>> hangs, I'm not really OK with this. >>>> >>>> These sporadic hangs you saw were on devices without an FPGA image directly >>>> accessing the SDRAM ports, right? >>>> >>>>> >>>>> Maybe the application of static config should happen in SPL, before the >>>>> DRAM is running, or something like that ? >>>> >>>> Thinking this further, limiting it to applying in SPL is not a good idea since >>>> that prevents us from implementing different FPGA images/configs by loading a >>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>> >>>> Would it work to make setting this optional, i.e. only write the bit if an FPGA >>>> config actually uses these ports? Then it couldn't lead to problems on other >>>> hardware... >>> >>> If the sporadic hangs issue happen on FPGA image that doesn't connect >>> to f2sdram interface, we can add the checking to only apply static cfg >>> when it has f2sdram port enabled. >>> It can send a patch with this checking for you to try if want. >> Well, what could cause that sporadic hang ? >> Yes, the hang happens on image which doesn't access the SDRAM IIRC. >> > Do you remember if the hang happen when run bridge enable/disable > command? Or other flow? FPGA bitstream was loaded via the fpga command , and then during the bridge enable it got stuck. > I have tested the following sequence 500 times with FPGA image that > doesn't contains fs2dram bridge, but didn't see the hang. > - program fpga image > - bridge enable > - write to h2f bridge > - read from h2f bridge > - bridge disable > - repeat step 1 The test we did also contained booting Linux inbetween, and then reboot through U-Boot, which loaded the bitstream , enabled bridges , started Linux, reboot etc.
On Mon, 2020-03-09 at 15:25 +0100, Marek Vasut wrote: > On 3/9/20 3:24 PM, Simon Goldschmidt wrote: > > On Mon, Mar 9, 2020 at 3:15 PM Marek Vasut <marex at denx.de> wrote: > > > On 3/9/20 3:10 PM, Simon Goldschmidt wrote: > > > > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut <marex at denx.de> wrote: > > > > > On 3/9/20 9:50 AM, Ley Foon Tan wrote: > > > > > > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen > > > > > > <dalon.westergreen at linux.intel.com> wrote: > > > > > > > I am reading through this thread, and want to point out that it is > > > > > > > not that the > > > > > > > FPGA bridge need be actively used in the fpga, but > > > > > > > rather that this port be configured in the FPGA > > > > > > > configuration. This is an > > > > > > > important distinction, ecery FPGA design that > > > > > > > instantiates the HPS does configure the F2S Bridge. it drives > > > > > > > select pins, > > > > > > > control pins, data pins, etc, on the interface to known values, > > > > > > > and so the apply can always be done as all SoC FPGA designs have > > > > > > > the soc > > > > > > > instantiated. If someone boots the arm, and uses an > > > > > > > FPGA design without having the soc instantiated, it may then cause > > > > > > > issues, but i > > > > > > > would argue that is not a supported use > > > > > > > in the first place. > > > > > > > > > > > > > > --dalon > > > > > > > > > > > > > > > > > > > I can reproduce the issue if without setting applycfg bit. Access to > > > > > > F2sdram interface will cause system hang. > > > > > > > > > > > > From the Cyclone 5 Soc datasheet: > > > > > > applycfg - Write with this bit set to apply all the settings loaded > > > > > > in > > > > > > SDR registers to the memory interface. This bit is write-only and > > > > > > always returns 0 if read. > > > > > > > > > > > > Software should set applycfg bit if change any register under SDR > > > > > > register range. SW is allowed to set this bit multiple times, the > > > > > > only > > > > > > condition is SDRAM need to be idle. > > > > > > My suggestion is we add back socfpga_sdram_apply_static_cfg(), but > > > > > > change the sequence to below: > > > > > > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); > > > > > > socfpga_sdram_apply_static_cfg(); > > > > > > > > > > > > Marek and Simon, are you okay with this? If yes, I will submit patch > > > > > > for this. > > > > > > > > > > The problem was that this was causing weird sporadic hangs on Gen5, > > > > > which is why it was removed. So until there is an explanation for > > > > > those > > > > > hangs, I'm not really OK with this. > > > > > > > > These sporadic hangs you saw were on devices without an FPGA image > > > > directly > > > > accessing the SDRAM ports, right? > > > > > > Yes > > > > > > > > Maybe the application of static config should happen in SPL, before > > > > > the > > > > > DRAM is running, or something like that ? > > > > > > > > Thinking this further, limiting it to applying in SPL is not a good idea > > > > since > > > > that prevents us from implementing different FPGA images/configs by > > > > loading a > > > > config later in the boot (i.e. in U-Boot from a FIT-image). > > > > > > Well, but later we have SDRAM running and we cannot make it go idle, can > > > we? > > > Unfortunately the sdram cfg apply must occur AFTER the fpga is configured. This is because the FPGA drives configuration bits, around the interfaces datawidth for example, that are used in setting up the dram interface. I believe the intent is for the command to only run when the ridge enable function is called. > > > > Would it work to make setting this optional, i.e. only write the bit if > > > > an FPGA > > > > config actually uses these ports? Then it couldn't lead to problems on > > > > other > > > > hardware... > > > > > > Can you make SDRAM bus really idle ? > > > > From the CPU side, that should work, no? Of course you have to make sure no > > other peripheraly (including FPGA!) are using the RAM. > > > > And if this would be an explicit command, people needing this could > > experiment with it - and hopefully give better hints as to what's going > > wrong > > if we *do* see problems again. > > Maybe altera has something hidden somewhere in the bus tunables ? :) The only trick i am aware of, and Ley Foon, please comment, is isolating relevant code to the caches before executing. --dalon
On 3/12/20 4:54 PM, Dalon L Westergreen wrote: [...] (thanks for fixing your mailer :)) >>>>>> >>>>>> The problem was that this was causing weird sporadic hangs on Gen5, >>>>>> which is why it was removed. So until there is an explanation for >>>>>> those >>>>>> hangs, I'm not really OK with this. >>>>> >>>>> These sporadic hangs you saw were on devices without an FPGA image >>>>> directly >>>>> accessing the SDRAM ports, right? >>>> >>>> Yes >>>> >>>>>> Maybe the application of static config should happen in SPL, before >>>>>> the >>>>>> DRAM is running, or something like that ? >>>>> >>>>> Thinking this further, limiting it to applying in SPL is not a good idea >>>>> since >>>>> that prevents us from implementing different FPGA images/configs by >>>>> loading a >>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>> >>>> Well, but later we have SDRAM running and we cannot make it go idle, can >>>> we? >>>> > > Unfortunately the sdram cfg apply must occur AFTER the fpga is configured. This > is because the FPGA drives configuration bits, around the interfaces datawidth > for example, that are used in setting up the dram interface. I believe the > intent is for the command to only run when the ridge enable function is called. So that's one part of the fix -- only run this apply_static_cfg if the bitstream uses the F2S bridge. >>>>> Would it work to make setting this optional, i.e. only write the bit if >>>>> an FPGA >>>>> config actually uses these ports? Then it couldn't lead to problems on >>>>> other >>>>> hardware... >>>> >>>> Can you make SDRAM bus really idle ? >>> >>> From the CPU side, that should work, no? Of course you have to make sure no >>> other peripheraly (including FPGA!) are using the RAM. >>> >>> And if this would be an explicit command, people needing this could >>> experiment with it - and hopefully give better hints as to what's going >>> wrong >>> if we *do* see problems again. >> >> Maybe altera has something hidden somewhere in the bus tunables ? :) > > The only trick i am aware of, and Ley Foon, please comment, is isolating > relevant code to the caches before executing. How do you make sure some DMA doesn't do something funny or some pending write doesn't trigger DRAM write ? There is more than the CPU that can access the DRAM and cause bus traffic.
On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: > On 3/12/20 4:54 PM, Dalon L Westergreen wrote: > [...] > > (thanks for fixing your mailer :)) > > > > > > > > The problem was that this was causing weird sporadic hangs on > > > > > > > Gen5, > > > > > > > which is why it was removed. So until there is an explanation for > > > > > > > those > > > > > > > hangs, I'm not really OK with this. > > > > > > > > > > > > These sporadic hangs you saw were on devices without an FPGA image > > > > > > directly > > > > > > accessing the SDRAM ports, right? > > > > > > > > > > Yes > > > > > > > > > > > > Maybe the application of static config should happen in SPL, > > > > > > > before > > > > > > > the > > > > > > > DRAM is running, or something like that ? > > > > > > > > > > > > Thinking this further, limiting it to applying in SPL is not a good > > > > > > idea > > > > > > since > > > > > > that prevents us from implementing different FPGA images/configs by > > > > > > loading a > > > > > > config later in the boot (i.e. in U-Boot from a FIT-image). > > > > > > > > > > Well, but later we have SDRAM running and we cannot make it go idle, > > > > > can > > > > > we? > > > > > > > > > Unfortunately the sdram cfg apply must occur AFTER the fpga is > > configured. This > > is because the FPGA drives configuration bits, around the interfaces > > datawidth > > for example, that are used in setting up the dram interface. I believe the > > intent is for the command to only run when the ridge enable function is > > called. > > So that's one part of the fix -- only run this apply_static_cfg if the > bitstream uses the F2S bridge. actually, the restriction is to apply this only if the FPGA is configured, whether the bridge is used is irrelevant. you can further restrict this to only when the bridge is used, but to me that means devicetree entries or something to determine whether it is used. > > > > > > > Would it work to make setting this optional, i.e. only write the bit > > > > > > if > > > > > > an FPGA > > > > > > config actually uses these ports? Then it couldn't lead to problems > > > > > > on > > > > > > other > > > > > > hardware... > > > > > > > > > > Can you make SDRAM bus really idle ? > > > > > > > > From the CPU side, that should work, no? Of course you have to make sure > > > > no > > > > other peripheraly (including FPGA!) are using the RAM. > > > > > > > > And if this would be an explicit command, people needing this could > > > > experiment with it - and hopefully give better hints as to what's going > > > > wrong > > > > if we *do* see problems again. > > > > > > Maybe altera has something hidden somewhere in the bus tunables ? :) > > > > The only trick i am aware of, and Ley Foon, please comment, is isolating > > relevant code to the caches before executing. > > How do you make sure some DMA doesn't do something funny or some pending > write doesn't trigger DRAM write ? There is more than the CPU that can > access the DRAM and cause bus traffic. True, and it is unclear how we could ensure there is absolutely no traffic. --dalon
Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: > > > On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >> [...] >> >> (thanks for fixing your mailer :)) >> >>>>>>>> The problem was that this was causing weird sporadic hangs on >>>>>>>> Gen5, >>>>>>>> which is why it was removed. So until there is an explanation for >>>>>>>> those >>>>>>>> hangs, I'm not really OK with this. >>>>>>> >>>>>>> These sporadic hangs you saw were on devices without an FPGA image >>>>>>> directly >>>>>>> accessing the SDRAM ports, right? >>>>>> >>>>>> Yes >>>>>> >>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>> before >>>>>>>> the >>>>>>>> DRAM is running, or something like that ? >>>>>>> >>>>>>> Thinking this further, limiting it to applying in SPL is not a good >>>>>>> idea >>>>>>> since >>>>>>> that prevents us from implementing different FPGA images/configs by >>>>>>> loading a >>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>> >>>>>> Well, but later we have SDRAM running and we cannot make it go idle, >>>>>> can >>>>>> we? >>>>>> >>> >>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>> configured. This >>> is because the FPGA drives configuration bits, around the interfaces >>> datawidth >>> for example, that are used in setting up the dram interface. I believe the >>> intent is for the command to only run when the ridge enable function is >>> called. >> >> So that's one part of the fix -- only run this apply_static_cfg if the >> bitstream uses the F2S bridge. > > actually, the restriction is to apply this only if the FPGA is configured, > whether the bridge is used is irrelevant. you can further restrict this > to only when the bridge is used, but to me that means devicetree entries > or something to determine whether it is used. In my opinion, we need an FPGA-specific devicetree (or something similar) to describe the FPGA image, anyway. Today, too much configuration is applied at compile time (or when programming SPL to flash at latest) - there's currently no way to switch peripherals to FPGA for one image but not for another, for example. Worse: if you enable bridges but there's no slave attached, the CPU can be stuck. That would need to be described with the FPGA image as well. Regards, Simon > >> >>>>>>> Would it work to make setting this optional, i.e. only write the bit >>>>>>> if >>>>>>> an FPGA >>>>>>> config actually uses these ports? Then it couldn't lead to problems >>>>>>> on >>>>>>> other >>>>>>> hardware... >>>>>> >>>>>> Can you make SDRAM bus really idle ? >>>>> >>>>> From the CPU side, that should work, no? Of course you have to make sure >>>>> no >>>>> other peripheraly (including FPGA!) are using the RAM. >>>>> >>>>> And if this would be an explicit command, people needing this could >>>>> experiment with it - and hopefully give better hints as to what's going >>>>> wrong >>>>> if we *do* see problems again. >>>> >>>> Maybe altera has something hidden somewhere in the bus tunables ? :) >>> >>> The only trick i am aware of, and Ley Foon, please comment, is isolating >>> relevant code to the caches before executing. >> >> How do you make sure some DMA doesn't do something funny or some pending >> write doesn't trigger DRAM write ? There is more than the CPU that can >> access the DRAM and cause bus traffic. > > True, and it is unclear how we could ensure there is absolutely no traffic. > > --dalon > >
On 3/16/20 8:04 PM, Simon Goldschmidt wrote: > Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: >> >> >> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >>> [...] >>> >>> (thanks for fixing your mailer :)) >>> >>>>>>>>> The problem was that this was causing weird sporadic hangs on >>>>>>>>> Gen5, >>>>>>>>> which is why it was removed. So until there is an explanation for >>>>>>>>> those >>>>>>>>> hangs, I'm not really OK with this. >>>>>>>> >>>>>>>> These sporadic hangs you saw were on devices without an FPGA image >>>>>>>> directly >>>>>>>> accessing the SDRAM ports, right? >>>>>>> >>>>>>> Yes >>>>>>> >>>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>>> before >>>>>>>>> the >>>>>>>>> DRAM is running, or something like that ? >>>>>>>> >>>>>>>> Thinking this further, limiting it to applying in SPL is not a good >>>>>>>> idea >>>>>>>> since >>>>>>>> that prevents us from implementing different FPGA images/configs by >>>>>>>> loading a >>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>>> >>>>>>> Well, but later we have SDRAM running and we cannot make it go idle, >>>>>>> can >>>>>>> we? >>>>>>> >>>> >>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>>> configured. This >>>> is because the FPGA drives configuration bits, around the interfaces >>>> datawidth >>>> for example, that are used in setting up the dram interface. I believe the >>>> intent is for the command to only run when the ridge enable function is >>>> called. >>> >>> So that's one part of the fix -- only run this apply_static_cfg if the >>> bitstream uses the F2S bridge. >> >> actually, the restriction is to apply this only if the FPGA is configured, >> whether the bridge is used is irrelevant. you can further restrict this >> to only when the bridge is used, but to me that means devicetree entries >> or something to determine whether it is used. > > In my opinion, we need an FPGA-specific devicetree (or something > similar) to describe the FPGA image, anyway. Like a DTO ? > Today, too much > configuration is applied at compile time (or when programming SPL to > flash at latest) - there's currently no way to switch peripherals to > FPGA for one image but not for another, for example. Yes > Worse: if you enable bridges but there's no slave attached, the CPU can > be stuck. That would need to be described with the FPGA image as well. Can you propose a patch ?
Am 16.03.2020 um 20:06 schrieb Marek Vasut: > On 3/16/20 8:04 PM, Simon Goldschmidt wrote: >> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: >>> >>> >>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >>>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >>>> [...] >>>> >>>> (thanks for fixing your mailer :)) >>>> >>>>>>>>>> The problem was that this was causing weird sporadic hangs on >>>>>>>>>> Gen5, >>>>>>>>>> which is why it was removed. So until there is an explanation for >>>>>>>>>> those >>>>>>>>>> hangs, I'm not really OK with this. >>>>>>>>> >>>>>>>>> These sporadic hangs you saw were on devices without an FPGA image >>>>>>>>> directly >>>>>>>>> accessing the SDRAM ports, right? >>>>>>>> >>>>>>>> Yes >>>>>>>> >>>>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>>>> before >>>>>>>>>> the >>>>>>>>>> DRAM is running, or something like that ? >>>>>>>>> >>>>>>>>> Thinking this further, limiting it to applying in SPL is not a good >>>>>>>>> idea >>>>>>>>> since >>>>>>>>> that prevents us from implementing different FPGA images/configs by >>>>>>>>> loading a >>>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>>>> >>>>>>>> Well, but later we have SDRAM running and we cannot make it go idle, >>>>>>>> can >>>>>>>> we? >>>>>>>> >>>>> >>>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>>>> configured. This >>>>> is because the FPGA drives configuration bits, around the interfaces >>>>> datawidth >>>>> for example, that are used in setting up the dram interface. I believe the >>>>> intent is for the command to only run when the ridge enable function is >>>>> called. >>>> >>>> So that's one part of the fix -- only run this apply_static_cfg if the >>>> bitstream uses the F2S bridge. >>> >>> actually, the restriction is to apply this only if the FPGA is configured, >>> whether the bridge is used is irrelevant. you can further restrict this >>> to only when the bridge is used, but to me that means devicetree entries >>> or something to determine whether it is used. >> >> In my opinion, we need an FPGA-specific devicetree (or something >> similar) to describe the FPGA image, anyway. > > Like a DTO ? > >> Today, too much >> configuration is applied at compile time (or when programming SPL to >> flash at latest) - there's currently no way to switch peripherals to >> FPGA for one image but not for another, for example. > > Yes > >> Worse: if you enable bridges but there's no slave attached, the CPU can >> be stuck. That would need to be described with the FPGA image as well. > > Can you propose a patch ? In corona times and with kids now at home, I don't know if I can soon :-( Regards, Simon
On 3/16/20 8:09 PM, Simon Goldschmidt wrote: [...] >>> Today, too much >>> configuration is applied at compile time (or when programming SPL to >>> flash at latest) - there's currently no way to switch peripherals to >>> FPGA for one image but not for another, for example. >> >> Yes >> >>> Worse: if you enable bridges but there's no slave attached, the CPU can >>> be stuck. That would need to be described with the FPGA image as well. >> >> Can you propose a patch ? > > In corona times and with kids now at home, I don't know if I can soon :-( The release is far away anyway :) We're already on full lockdown, hopefully it goes away soon.
On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote: > On 3/16/20 8:04 PM, Simon Goldschmidt wrote: > > Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: > > > > > > On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: > > > > On 3/12/20 4:54 PM, Dalon L Westergreen wrote: > > > > [...] > > > > > > > > (thanks for fixing your mailer :)) > > > > > > > > > > > > > > The problem was that this was causing weird sporadic hangs > > > > > > > > > > on > > > > > > > > > > Gen5, > > > > > > > > > > which is why it was removed. So until there is an > > > > > > > > > > explanation for > > > > > > > > > > those > > > > > > > > > > hangs, I'm not really OK with this. > > > > > > > > > > > > > > > > > > These sporadic hangs you saw were on devices without an FPGA > > > > > > > > > image > > > > > > > > > directly > > > > > > > > > accessing the SDRAM ports, right? > > > > > > > > > > > > > > > > Yes > > > > > > > > > > > > > > > > > > Maybe the application of static config should happen in SPL, > > > > > > > > > > before > > > > > > > > > > the > > > > > > > > > > DRAM is running, or something like that ? > > > > > > > > > > > > > > > > > > Thinking this further, limiting it to applying in SPL is not a > > > > > > > > > good > > > > > > > > > idea > > > > > > > > > since > > > > > > > > > that prevents us from implementing different FPGA > > > > > > > > > images/configs by > > > > > > > > > loading a > > > > > > > > > config later in the boot (i.e. in U-Boot from a FIT-image). > > > > > > > > > > > > > > > > Well, but later we have SDRAM running and we cannot make it go > > > > > > > > idle, > > > > > > > > can > > > > > > > > we? > > > > > > > > > > > > > > > > > > Unfortunately the sdram cfg apply must occur AFTER the fpga is > > > > > configured. This > > > > > is because the FPGA drives configuration bits, around the interfaces > > > > > datawidth > > > > > for example, that are used in setting up the dram interface. I > > > > > believe the > > > > > intent is for the command to only run when the ridge enable function > > > > > is > > > > > called. > > > > > > > > So that's one part of the fix -- only run this apply_static_cfg if the > > > > bitstream uses the F2S bridge. > > > > > > actually, the restriction is to apply this only if the FPGA is configured, > > > whether the bridge is used is irrelevant. you can further restrict this > > > to only when the bridge is used, but to me that means devicetree entries > > > or something to determine whether it is used. > > > > In my opinion, we need an FPGA-specific devicetree (or something > > similar) to describe the FPGA image, anyway. > > Like a DTO ? DTOs are how i suggest solving this in linux, so i would assume a dto would be best here too. > > > Today, too much > > configuration is applied at compile time (or when programming SPL to > > flash at latest) - there's currently no way to switch peripherals to > > FPGA for one image but not for another, for example. > > Yes > > > Worse: if you enable bridges but there's no slave attached, the CPU can > > be stuck. That would need to be described with the FPGA image as well. > > Can you propose a patch ? >
Am 16.03.2020 um 20:55 schrieb Dalon L Westergreen: > > > On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote: >> On 3/16/20 8:04 PM, Simon Goldschmidt wrote: >>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: >>>> >>>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: >>>>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: >>>>> [...] >>>>> >>>>> (thanks for fixing your mailer :)) >>>>> >>>>>>>>>>> The problem was that this was causing weird sporadic hangs >>>>>>>>>>> on >>>>>>>>>>> Gen5, >>>>>>>>>>> which is why it was removed. So until there is an >>>>>>>>>>> explanation for >>>>>>>>>>> those >>>>>>>>>>> hangs, I'm not really OK with this. >>>>>>>>>> >>>>>>>>>> These sporadic hangs you saw were on devices without an FPGA >>>>>>>>>> image >>>>>>>>>> directly >>>>>>>>>> accessing the SDRAM ports, right? >>>>>>>>> >>>>>>>>> Yes >>>>>>>>> >>>>>>>>>>> Maybe the application of static config should happen in SPL, >>>>>>>>>>> before >>>>>>>>>>> the >>>>>>>>>>> DRAM is running, or something like that ? >>>>>>>>>> >>>>>>>>>> Thinking this further, limiting it to applying in SPL is not a >>>>>>>>>> good >>>>>>>>>> idea >>>>>>>>>> since >>>>>>>>>> that prevents us from implementing different FPGA >>>>>>>>>> images/configs by >>>>>>>>>> loading a >>>>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). >>>>>>>>> >>>>>>>>> Well, but later we have SDRAM running and we cannot make it go >>>>>>>>> idle, >>>>>>>>> can >>>>>>>>> we? >>>>>>>>> >>>>>> >>>>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is >>>>>> configured. This >>>>>> is because the FPGA drives configuration bits, around the interfaces >>>>>> datawidth >>>>>> for example, that are used in setting up the dram interface. I >>>>>> believe the >>>>>> intent is for the command to only run when the ridge enable function >>>>>> is >>>>>> called. >>>>> >>>>> So that's one part of the fix -- only run this apply_static_cfg if the >>>>> bitstream uses the F2S bridge. >>>> >>>> actually, the restriction is to apply this only if the FPGA is configured, >>>> whether the bridge is used is irrelevant. you can further restrict this >>>> to only when the bridge is used, but to me that means devicetree entries >>>> or something to determine whether it is used. >>> >>> In my opinion, we need an FPGA-specific devicetree (or something >>> similar) to describe the FPGA image, anyway. >> >> Like a DTO ? > > DTOs are how i suggest solving this in linux, so i would assume a dto would > be best here too. Yes. That DTO should be beside the FPGA image, either in a FIT image or just loaded separately. It should contain pin settings, bridge settings etc. However, to ensure the bus is idle, we still would have to limit applying that config bit to before RAM is set up, so quite early in SPL, right? I cannot see how that would work, given the limit of 64K. Plus it's kind of a bad boot flow to configure the FPGA before even starting U-Boot... Regards, Simon > >> >>> Today, too much >>> configuration is applied at compile time (or when programming SPL to >>> flash at latest) - there's currently no way to switch peripherals to >>> FPGA for one image but not for another, for example. >> >> Yes >> >>> Worse: if you enable bridges but there's no slave attached, the CPU can >>> be stuck. That would need to be described with the FPGA image as well. >> >> Can you propose a patch ? >> >
On Tue, Mar 17, 2020 at 4:01 AM Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com> wrote: > > Am 16.03.2020 um 20:55 schrieb Dalon L Westergreen: > > > > > > On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote: > >> On 3/16/20 8:04 PM, Simon Goldschmidt wrote: > >>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen: > >>>> > >>>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote: > >>>>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote: > >>>>> [...] > >>>>> > >>>>> (thanks for fixing your mailer :)) > >>>>> > >>>>>>>>>>> The problem was that this was causing weird sporadic hangs > >>>>>>>>>>> on > >>>>>>>>>>> Gen5, > >>>>>>>>>>> which is why it was removed. So until there is an > >>>>>>>>>>> explanation for > >>>>>>>>>>> those > >>>>>>>>>>> hangs, I'm not really OK with this. > >>>>>>>>>> > >>>>>>>>>> These sporadic hangs you saw were on devices without an FPGA > >>>>>>>>>> image > >>>>>>>>>> directly > >>>>>>>>>> accessing the SDRAM ports, right? > >>>>>>>>> > >>>>>>>>> Yes > >>>>>>>>> > >>>>>>>>>>> Maybe the application of static config should happen in SPL, > >>>>>>>>>>> before > >>>>>>>>>>> the > >>>>>>>>>>> DRAM is running, or something like that ? > >>>>>>>>>> > >>>>>>>>>> Thinking this further, limiting it to applying in SPL is not a > >>>>>>>>>> good > >>>>>>>>>> idea > >>>>>>>>>> since > >>>>>>>>>> that prevents us from implementing different FPGA > >>>>>>>>>> images/configs by > >>>>>>>>>> loading a > >>>>>>>>>> config later in the boot (i.e. in U-Boot from a FIT-image). > >>>>>>>>> > >>>>>>>>> Well, but later we have SDRAM running and we cannot make it go > >>>>>>>>> idle, > >>>>>>>>> can > >>>>>>>>> we? > >>>>>>>>> > >>>>>> > >>>>>> Unfortunately the sdram cfg apply must occur AFTER the fpga is > >>>>>> configured. This > >>>>>> is because the FPGA drives configuration bits, around the interfaces > >>>>>> datawidth > >>>>>> for example, that are used in setting up the dram interface. I > >>>>>> believe the > >>>>>> intent is for the command to only run when the ridge enable function > >>>>>> is > >>>>>> called. > >>>>> > >>>>> So that's one part of the fix -- only run this apply_static_cfg if the > >>>>> bitstream uses the F2S bridge. > >>>> > >>>> actually, the restriction is to apply this only if the FPGA is configured, > >>>> whether the bridge is used is irrelevant. you can further restrict this > >>>> to only when the bridge is used, but to me that means devicetree entries > >>>> or something to determine whether it is used. > >>> > >>> In my opinion, we need an FPGA-specific devicetree (or something > >>> similar) to describe the FPGA image, anyway. > >> > >> Like a DTO ? > > > > DTOs are how i suggest solving this in linux, so i would assume a dto would > > be best here too. > > Yes. That DTO should be beside the FPGA image, either in a FIT image or > just loaded separately. It should contain pin settings, bridge settings etc. > > However, to ensure the bus is idle, we still would have to limit > applying that config bit to before RAM is set up, so quite early in SPL, > right? I cannot see how that would work, given the limit of 64K. Plus > it's kind of a bad boot flow to configure the FPGA before even starting > U-Boot... There is usecase user may want to program fpga image in Uboot command prompt. It will have problem too. socfpga_sdram_apply_static_cfg() is written in assembly code and the code is fit to one cacheline size (32 bytes). This at least make sure CPU no access to SDRAM when run apply static cfg code in uboot. Frankly, this can't prevent external master access to SDRAM. Marek, I found code in drivers/fpga/socfpga_gen5.c:socfpga_load() write to SDR_CTRLGRP_FPGAPORTRST_ADDRESS register, but doesn't write to call to socfpga_sdram_apply_static_cfg() function. This means FPGA port is not put into reset before program fpga image. Suspect this might reason it cause sporadic hangs. Stay safe everyone. Regards Ley Foon
On Fri, Mar 20, 2020 at 3:52 PM Ley Foon Tan <lftan.linux at gmail.com> wrote: > > >>>>>> configured. This > > >>>>>> is because the FPGA drives configuration bits, around the interfaces > > >>>>>> datawidth > > >>>>>> for example, that are used in setting up the dram interface. I > > >>>>>> believe the > > >>>>>> intent is for the command to only run when the ridge enable function > > >>>>>> is > > >>>>>> called. > > >>>>> > > >>>>> So that's one part of the fix -- only run this apply_static_cfg if the > > >>>>> bitstream uses the F2S bridge. > > >>>> > > >>>> actually, the restriction is to apply this only if the FPGA is configured, > > >>>> whether the bridge is used is irrelevant. you can further restrict this > > >>>> to only when the bridge is used, but to me that means devicetree entries > > >>>> or something to determine whether it is used. > > >>> > > >>> In my opinion, we need an FPGA-specific devicetree (or something > > >>> similar) to describe the FPGA image, anyway. > > >> > > >> Like a DTO ? > > > > > > DTOs are how i suggest solving this in linux, so i would assume a dto would > > > be best here too. > > > > Yes. That DTO should be beside the FPGA image, either in a FIT image or > > just loaded separately. It should contain pin settings, bridge settings etc. > > > > However, to ensure the bus is idle, we still would have to limit > > applying that config bit to before RAM is set up, so quite early in SPL, > > right? I cannot see how that would work, given the limit of 64K. Plus > > it's kind of a bad boot flow to configure the FPGA before even starting > > U-Boot... > There is usecase user may want to program fpga image in Uboot command > prompt. It will have problem too. > > socfpga_sdram_apply_static_cfg() is written in assembly code and the > code is fit to one cacheline size (32 bytes). This at least make sure > CPU no access to SDRAM when run apply static cfg code in uboot. > Frankly, this can't prevent external master access to SDRAM. > > Marek, > I found code in drivers/fpga/socfpga_gen5.c:socfpga_load() write to > SDR_CTRLGRP_FPGAPORTRST_ADDRESS register, but doesn't write to call to > socfpga_sdram_apply_static_cfg() function. This means FPGA port is not > put into reset before program fpga image. Suspect this might reason it > cause sporadic hangs. > > Stay safe everyone. > > Regards > Ley Foon Hi Cyclone5 F2sdram interface is totally broken in uboot now, can we revert back the socfpga_sdram_apply_static_cfg() but add checking if f2sdram bridge is enabled. Also add call to socfpga_sdram_apply_static_cfg() in socfpga_load(). Simon's enhancement for DTO might not getting in soon. Thanks. Regards Ley Foon
On 3/31/20 10:13 AM, Ley Foon Tan wrote: > On Fri, Mar 20, 2020 at 3:52 PM Ley Foon Tan <lftan.linux at gmail.com> wrote: > >>>>>>>>> configured. This >>>>>>>>> is because the FPGA drives configuration bits, around the interfaces >>>>>>>>> datawidth >>>>>>>>> for example, that are used in setting up the dram interface. I >>>>>>>>> believe the >>>>>>>>> intent is for the command to only run when the ridge enable function >>>>>>>>> is >>>>>>>>> called. >>>>>>>> >>>>>>>> So that's one part of the fix -- only run this apply_static_cfg if the >>>>>>>> bitstream uses the F2S bridge. >>>>>>> >>>>>>> actually, the restriction is to apply this only if the FPGA is configured, >>>>>>> whether the bridge is used is irrelevant. you can further restrict this >>>>>>> to only when the bridge is used, but to me that means devicetree entries >>>>>>> or something to determine whether it is used. >>>>>> >>>>>> In my opinion, we need an FPGA-specific devicetree (or something >>>>>> similar) to describe the FPGA image, anyway. >>>>> >>>>> Like a DTO ? >>>> >>>> DTOs are how i suggest solving this in linux, so i would assume a dto would >>>> be best here too. >>> >>> Yes. That DTO should be beside the FPGA image, either in a FIT image or >>> just loaded separately. It should contain pin settings, bridge settings etc. >>> >>> However, to ensure the bus is idle, we still would have to limit >>> applying that config bit to before RAM is set up, so quite early in SPL, >>> right? I cannot see how that would work, given the limit of 64K. Plus >>> it's kind of a bad boot flow to configure the FPGA before even starting >>> U-Boot... >> There is usecase user may want to program fpga image in Uboot command >> prompt. It will have problem too. >> >> socfpga_sdram_apply_static_cfg() is written in assembly code and the >> code is fit to one cacheline size (32 bytes). This at least make sure >> CPU no access to SDRAM when run apply static cfg code in uboot. >> Frankly, this can't prevent external master access to SDRAM. >> >> Marek, >> I found code in drivers/fpga/socfpga_gen5.c:socfpga_load() write to >> SDR_CTRLGRP_FPGAPORTRST_ADDRESS register, but doesn't write to call to >> socfpga_sdram_apply_static_cfg() function. This means FPGA port is not >> put into reset before program fpga image. Suspect this might reason it >> cause sporadic hangs. >> >> Stay safe everyone. >> >> Regards >> Ley Foon > > Hi > > Cyclone5 F2sdram interface is totally broken in uboot now, can we > revert back the socfpga_sdram_apply_static_cfg() but add checking if > f2sdram bridge is enabled. Also add call to > socfpga_sdram_apply_static_cfg() in socfpga_load(). > Simon's enhancement for DTO might not getting in soon. Is it better if it's totally and visibly broken, or if every 500 or so reboots the machine randomly and inobviously hangs when enabling bridges ? Also, there is still the problem where we are not able to guarantee that the DRAM bus will be completely idle before running the apply static cfg, or did that get sorted out somehow ? I think we shouldn't revert it, but rather make it somehow conditional, maybe by adding argument to the 'bridge' command or an environment variable (probably better), at least for this release.
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 22042d0de0..19c6d24170 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -213,6 +213,35 @@ static struct socfpga_reset_manager *reset_manager_base = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; +static void socfpga_sdram_apply_static_cfg(void) +{ + const u32 applymask = 0x8; + u32 val = readl(&sdr_ctrl->static_cfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); +} + void do_bridge_reset(int enable, unsigned int mask) {