diff mbox series

[v2,1/5] dt-bindings: prci: add indexes for reset signals available in prci

Message ID 1593087941-16872-2-git-send-email-sagar.kadam@sifive.com
State New
Headers show
Series add DM based reset driver for SiFive SoC's | expand

Commit Message

Sagar Shrikant Kadam June 25, 2020, 12:25 p.m. UTC 
Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
Reviewed-by: Bin Meng <bin.meng at windriver.com>
---
 include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Jagan Teki June 25, 2020, 5:43 p.m. UTC | #1 
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam
<sagar.kadam at sifive.com> wrote:
>
> Add bit indexes for reset signals within the PRCI module
> on FU540-C000 SoC.
> The DDR and ethernet sub-system's have reset signals
> indicated by these reset indexes.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> Reviewed-by: Bin Meng <bin.meng at windriver.com>
> ---
>  include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
> index 6a0b70a..1c03b09 100644
> --- a/include/dt-bindings/clock/sifive-fu540-prci.h
> +++ b/include/dt-bindings/clock/sifive-fu540-prci.h
> @@ -15,4 +15,12 @@
>  #define PRCI_CLK_GEMGXLPLL            2
>  #define PRCI_CLK_TLCLK                3
>
> +/* Reset bit indexes to be used by driver */
> +#define PRCI_RST_DDR_CTRL_N    0
> +#define PRCI_RST_DDR_AXI_N     1
> +#define PRCI_RST_DDR_AHB_N     2
> +#define PRCI_RST_DDR_PHY_N     3
> +/* bit 4 is reserved bit */
> +#define PRCI_RST_RSVD_N                4
> +#define PRCI_RST_GEMGXL_N      5
>  #endif

Do these bindings are synced from Linux? If Yes better to sync with a
particular commit or tag rather than patch.

Jagan.
Sagar Shrikant Kadam June 26, 2020, 3:21 a.m. UTC | #2 
Hi Jagan,

> -----Original Message-----
> From: Jagan Teki <jagan at amarulasolutions.com>
> Sent: Thursday, June 25, 2020 11:13 PM
> To: Sagar Kadam <sagar.kadam at sifive.com>
> Cc: U-Boot-Denx <u-boot at lists.denx.de>; Rick Chen <rick at andestech.com>;
> Paul Walmsley ( Sifive) <paul.walmsley at sifive.com>; Palmer Dabbelt
> <palmer at dabbelt.com>; Anup Patel <anup.patel at wdc.com>; Atish Patra
> <atish.patra at wdc.com>; Lukasz Majewski <lukma at denx.de>; Pragnesh
> Patel <pragnesh.patel at sifive.com>; bin.meng at windriver.com; Simon Glass
> <sjg at chromium.org>; Trevor Woerner <twoerner at gmail.com>; Eugeniy
> Paltsev <Eugeniy.Paltsev at synopsys.com>; Patrick Wildt
> <patrick at blueri.se>; Weijie Gao <weijie.gao at mediatek.com>; Fabio
> Estevam <festevam at gmail.com>
> Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals
> available in prci
> 
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
> 
> On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam
> <sagar.kadam at sifive.com> wrote:
> >
> > Add bit indexes for reset signals within the PRCI module
> > on FU540-C000 SoC.
> > The DDR and ethernet sub-system's have reset signals
> > indicated by these reset indexes.
> >
> > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> > Reviewed-by: Bin Meng <bin.meng at windriver.com>
> > ---
> >  include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
> bindings/clock/sifive-fu540-prci.h
> > index 6a0b70a..1c03b09 100644
> > --- a/include/dt-bindings/clock/sifive-fu540-prci.h
> > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h
> > @@ -15,4 +15,12 @@
> >  #define PRCI_CLK_GEMGXLPLL            2
> >  #define PRCI_CLK_TLCLK                3
> >
> > +/* Reset bit indexes to be used by driver */
> > +#define PRCI_RST_DDR_CTRL_N    0
> > +#define PRCI_RST_DDR_AXI_N     1
> > +#define PRCI_RST_DDR_AHB_N     2
> > +#define PRCI_RST_DDR_PHY_N     3
> > +/* bit 4 is reserved bit */
> > +#define PRCI_RST_RSVD_N                4
> > +#define PRCI_RST_GEMGXL_N      5
> >  #endif
> 
> Do these bindings are synced from Linux? If Yes better to sync with a
> particular commit or tag rather than patch.
>

No, these reset bindings are not synced from Linux.

Thanks & Regards,
Sagar
 
> Jagan.
Jagan Teki June 29, 2020, 3:30 p.m. UTC | #3 
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam at sifive.com> wrote:
>
> Hi Jagan,
>
> > -----Original Message-----
> > From: Jagan Teki <jagan at amarulasolutions.com>
> > Sent: Thursday, June 25, 2020 11:13 PM
> > To: Sagar Kadam <sagar.kadam at sifive.com>
> > Cc: U-Boot-Denx <u-boot at lists.denx.de>; Rick Chen <rick at andestech.com>;
> > Paul Walmsley ( Sifive) <paul.walmsley at sifive.com>; Palmer Dabbelt
> > <palmer at dabbelt.com>; Anup Patel <anup.patel at wdc.com>; Atish Patra
> > <atish.patra at wdc.com>; Lukasz Majewski <lukma at denx.de>; Pragnesh
> > Patel <pragnesh.patel at sifive.com>; bin.meng at windriver.com; Simon Glass
> > <sjg at chromium.org>; Trevor Woerner <twoerner at gmail.com>; Eugeniy
> > Paltsev <Eugeniy.Paltsev at synopsys.com>; Patrick Wildt
> > <patrick at blueri.se>; Weijie Gao <weijie.gao at mediatek.com>; Fabio
> > Estevam <festevam at gmail.com>
> > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals
> > available in prci
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam
> > <sagar.kadam at sifive.com> wrote:
> > >
> > > Add bit indexes for reset signals within the PRCI module
> > > on FU540-C000 SoC.
> > > The DDR and ethernet sub-system's have reset signals
> > > indicated by these reset indexes.
> > >
> > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> > > Reviewed-by: Bin Meng <bin.meng at windriver.com>
> > > ---
> > >  include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++
> > >  1 file changed, 8 insertions(+)
> > >
> > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
> > bindings/clock/sifive-fu540-prci.h
> > > index 6a0b70a..1c03b09 100644
> > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h
> > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h
> > > @@ -15,4 +15,12 @@
> > >  #define PRCI_CLK_GEMGXLPLL            2
> > >  #define PRCI_CLK_TLCLK                3
> > >
> > > +/* Reset bit indexes to be used by driver */
> > > +#define PRCI_RST_DDR_CTRL_N    0
> > > +#define PRCI_RST_DDR_AXI_N     1
> > > +#define PRCI_RST_DDR_AHB_N     2
> > > +#define PRCI_RST_DDR_PHY_N     3
> > > +/* bit 4 is reserved bit */
> > > +#define PRCI_RST_RSVD_N                4
> > > +#define PRCI_RST_GEMGXL_N      5
> > >  #endif
> >
> > Do these bindings are synced from Linux? If Yes better to sync with a
> > particular commit or tag rather than patch.
> >
>
> No, these reset bindings are not synced from Linux.

This is synced file from Linux, better to inline with Linux files
always, if these bindings are not related to Linux then maintain it in
a separate file or support it in Linux first if they do require for
Linux.

Jagan.
Sagar Shrikant Kadam June 29, 2020, 4:07 p.m. UTC | #4 
Hello Jagan,
> -----Original Message-----
> From: Jagan Teki <jagan at amarulasolutions.com>
> Sent: Monday, June 29, 2020 9:00 PM
> To: Sagar Kadam <sagar.kadam at sifive.com>
> Cc: U-Boot-Denx <u-boot at lists.denx.de>; Rick Chen <rick at andestech.com>;
> Paul Walmsley ( Sifive) <paul.walmsley at sifive.com>; Palmer Dabbelt
> <palmer at dabbelt.com>; Anup Patel <anup.patel at wdc.com>; Atish Patra
> <atish.patra at wdc.com>; Lukasz Majewski <lukma at denx.de>; Pragnesh
> Patel <pragnesh.patel at sifive.com>; bin.meng at windriver.com; Simon Glass
> <sjg at chromium.org>; Trevor Woerner <twoerner at gmail.com>; Eugeniy
> Paltsev <Eugeniy.Paltsev at synopsys.com>; Patrick Wildt
> <patrick at blueri.se>; Weijie Gao <weijie.gao at mediatek.com>; Fabio
> Estevam <festevam at gmail.com>
> Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals
> available in prci
> 
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
> 
> On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam <sagar.kadam at sifive.com>
> wrote:
> >
> > Hi Jagan,
> >
> > > -----Original Message-----
> > > From: Jagan Teki <jagan at amarulasolutions.com>
> > > Sent: Thursday, June 25, 2020 11:13 PM
> > > To: Sagar Kadam <sagar.kadam at sifive.com>
> > > Cc: U-Boot-Denx <u-boot at lists.denx.de>; Rick Chen
> <rick at andestech.com>;
> > > Paul Walmsley ( Sifive) <paul.walmsley at sifive.com>; Palmer Dabbelt
> > > <palmer at dabbelt.com>; Anup Patel <anup.patel at wdc.com>; Atish
> Patra
> > > <atish.patra at wdc.com>; Lukasz Majewski <lukma at denx.de>; Pragnesh
> > > Patel <pragnesh.patel at sifive.com>; bin.meng at windriver.com; Simon
> Glass
> > > <sjg at chromium.org>; Trevor Woerner <twoerner at gmail.com>; Eugeniy
> > > Paltsev <Eugeniy.Paltsev at synopsys.com>; Patrick Wildt
> > > <patrick at blueri.se>; Weijie Gao <weijie.gao at mediatek.com>; Fabio
> > > Estevam <festevam at gmail.com>
> > > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset
> signals
> > > available in prci
> > >
> > > [External Email] Do not click links or attachments unless you recognize
> the
> > > sender and know the content is safe
> > >
> > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam
> > > <sagar.kadam at sifive.com> wrote:
> > > >
> > > > Add bit indexes for reset signals within the PRCI module
> > > > on FU540-C000 SoC.
> > > > The DDR and ethernet sub-system's have reset signals
> > > > indicated by these reset indexes.
> > > >
> > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>
> > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>
> > > > Reviewed-by: Bin Meng <bin.meng at windriver.com>
> > > > ---
> > > >  include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++
> > > >  1 file changed, 8 insertions(+)
> > > >
> > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
> > > bindings/clock/sifive-fu540-prci.h
> > > > index 6a0b70a..1c03b09 100644
> > > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h
> > > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h
> > > > @@ -15,4 +15,12 @@
> > > >  #define PRCI_CLK_GEMGXLPLL            2
> > > >  #define PRCI_CLK_TLCLK                3
> > > >
> > > > +/* Reset bit indexes to be used by driver */
> > > > +#define PRCI_RST_DDR_CTRL_N    0
> > > > +#define PRCI_RST_DDR_AXI_N     1
> > > > +#define PRCI_RST_DDR_AHB_N     2
> > > > +#define PRCI_RST_DDR_PHY_N     3
> > > > +/* bit 4 is reserved bit */
> > > > +#define PRCI_RST_RSVD_N                4
> > > > +#define PRCI_RST_GEMGXL_N      5
> > > >  #endif
> > >
> > > Do these bindings are synced from Linux? If Yes better to sync with a
> > > particular commit or tag rather than patch.
> > >
> >
> > No, these reset bindings are not synced from Linux.
> 
> This is synced file from Linux, better to inline with Linux files
> always, if these bindings are not related to Linux then maintain it in
> a separate file or support it in Linux first if they do require for
> Linux.
> 
Ohh. Sorry I thought you were asking if reset-bindings are from Linux.
Yes this file is synced from Linux but these reset-bindings are not related
to Linux. So I can split it and place reset bindings into another file:
"include/dt-bindings/reset/sifive-fu540-reset.h"
and include it wherever required.  Please let me know if this sounds okay.

Thanks & BR,
Sagar Kadam

> Jagan.
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644
--- a/include/dt-bindings/clock/sifive-fu540-prci.h
+++ b/include/dt-bindings/clock/sifive-fu540-prci.h
@@ -15,4 +15,12 @@ 
 #define PRCI_CLK_GEMGXLPLL	       2
 #define PRCI_CLK_TLCLK		       3
 
+/* Reset bit indexes to be used by driver */
+#define PRCI_RST_DDR_CTRL_N	0
+#define PRCI_RST_DDR_AXI_N	1
+#define PRCI_RST_DDR_AHB_N	2
+#define PRCI_RST_DDR_PHY_N	3
+/* bit 4 is reserved bit */
+#define PRCI_RST_RSVD_N		4
+#define PRCI_RST_GEMGXL_N	5
 #endif