Message ID | 1592828876-7724-3-git-send-email-sagar.kadam@sifive.com |
---|---|
State | Superseded |
Headers | show |
Series | add DM based reset driver for SiFive SoC's | expand |
On Mon, Jun 22, 2020 at 8:28 PM Sagar Shrikant Kadam <sagar.kadam at sifive.com> wrote: > > Indexes of reset signals available in PRCI driver are also > defined in include/dt-bindings/clock/sifive-fu540-prci.h. > So use those instead of defining new ones again within the > fu540-prci driver. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>[A > --- > drivers/clk/sifive/fu540-prci.c | 16 ++++++---------- > 1 file changed, 6 insertions(+), 10 deletions(-) > Reviewed-by: Bin Meng <bin.meng at windriver.com>
On Wed, Jun 24, 2020 at 11:01 AM Bin Meng <bmeng.cn at gmail.com> wrote: > > On Mon, Jun 22, 2020 at 8:28 PM Sagar Shrikant Kadam > <sagar.kadam at sifive.com> wrote: > > > > Indexes of reset signals available in PRCI driver are also > > defined in include/dt-bindings/clock/sifive-fu540-prci.h. > > So use those instead of defining new ones again within the > > fu540-prci driver. > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>[A Forget to mention, please fix the [A in the next version > > --- > > drivers/clk/sifive/fu540-prci.c | 16 ++++++---------- > > 1 file changed, 6 insertions(+), 10 deletions(-) > > > > Reviewed-by: Bin Meng <bin.meng at windriver.com>
Hi, > -----Original Message----- > From: Bin Meng <bmeng.cn at gmail.com> > Sent: Wednesday, June 24, 2020 8:33 AM > To: Sagar Kadam <sagar.kadam at sifive.com> > Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Rick Chen > <rick at andestech.com>; Paul Walmsley ( Sifive) > <paul.walmsley at sifive.com>; Palmer Dabbelt <palmer at dabbelt.com>; > Anup Patel <anup.patel at wdc.com>; Atish Patra <atish.patra at wdc.com>; > Lukasz Majewski <lukma at denx.de>; Pragnesh Patel > <pragnesh.patel at sifive.com>; Jagan Teki <jagan at amarulasolutions.com>; > Simon Glass <sjg at chromium.org>; twoerner at gmail.com; Patrick Wildt > <patrick at blueri.se>; Fabio Estevam <festevam at gmail.com>; Weijie Gao > <weijie.gao at mediatek.com>; Eugeniy Paltsev > <Eugeniy.Paltsev at synopsys.com> > Subject: Re: [PATCH 2/5] fu540: prci: use common reset indexes defined in > binding header > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Wed, Jun 24, 2020 at 11:01 AM Bin Meng <bmeng.cn at gmail.com> > wrote: > > > > On Mon, Jun 22, 2020 at 8:28 PM Sagar Shrikant Kadam > > <sagar.kadam at sifive.com> wrote: > > > > > > Indexes of reset signals available in PRCI driver are also defined > > > in include/dt-bindings/clock/sifive-fu540-prci.h. > > > So use those instead of defining new ones again within the > > > fu540-prci driver. > > > > > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> > > > Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>[A > > Forget to mention, please fix the [A in the next version > I will update fix for "[A". > > > --- > > > drivers/clk/sifive/fu540-prci.c | 16 ++++++---------- > > > 1 file changed, 6 insertions(+), 10 deletions(-) > > > > > > > Reviewed-by: Bin Meng <bin.meng at windriver.com> Thanks & BR, Sagar
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index fe6e0d4..57d811e 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -131,21 +131,17 @@ /* DEVICESRESETREG */ #define PRCI_DEVICESRESETREG_OFFSET 0x28 -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 + #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 + (0x1 << PRCI_RST_DDR_CTRL_N) #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 + (0x1 << PRCI_RST_DDR_AXI_N) #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 + (0x1 << PRCI_RST_DDR_AHB_N) #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 + (0x1 << PRCI_RST_DDR_PHY_N) #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) + (0x1 << PRCI_RST_GEMGXL_N) /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c