| Message ID | 20200606171534.736365-3-ardb@kernel.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fixes for running U-boot under QEMU/KVM | expand |
On 6/6/20 7:15 PM, Ard Biesheuvel wrote: > QEMU's mach-virt machine only supports selecting CPU models that > implement the virtualization extensions, and are therefore guaranteed > to support LPAE as well. I wonder why qemu-system-arm -machine virt -cpu help lists cortex-a9 (which is not LPAE enabled). But when I try to use it I get qemu-system-arm: mach-virt: CPU type cortex-a9-arm-cpu not supported This looks like a missing feature in QEMU. The default CPU for machine=virt is arm,cortex-a15. Acked-by: Heinrich Schuchardt <xypron.glpk at gmx.de. > > Initially, QEMU would not allow emulating these CPUs running in HYP > mode (or EL2, for AArch64), but today, it also contains a complete > implementation of the virtualization extensions themselves. > > This means we could be running U-Boot in HYP mode, in which case the > LPAE long descriptor page table format is the only format that is > supported. If we are not running in HYP mode, we can use either. > > So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we > get the best support for running with the MMU and caches enabled at > any privilege level. > > Signed-off-by: Ard Biesheuvel <ardb at kernel.org> > --- > configs/qemu_arm_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig > index a8473988bd76..75bdce7708c7 100644 > --- a/configs/qemu_arm_defconfig > +++ b/configs/qemu_arm_defconfig > @@ -1,5 +1,6 @@ > CONFIG_ARM=y > CONFIG_ARM_SMCCC=y > +CONFIG_ARMV7_LPAE=y > CONFIG_ARCH_QEMU=y > CONFIG_ENV_SIZE=0x40000 > CONFIG_ENV_SECT_SIZE=0x40000 >
On 6/6/20 10:32 PM, Heinrich Schuchardt wrote: > On 6/6/20 7:15 PM, Ard Biesheuvel wrote: >> QEMU's mach-virt machine only supports selecting CPU models that >> implement the virtualization extensions, and are therefore guaranteed >> to support LPAE as well. > > I wonder why > qemu-system-arm -machine virt -cpu help > lists cortex-a9 (which is not LPAE enabled). > > But when I try to use it I get > qemu-system-arm: mach-virt: CPU type cortex-a9-arm-cpu not supported > This looks like a missing feature in QEMU. > > The default CPU for machine=virt is arm,cortex-a15. > > Acked-by: Heinrich Schuchardt <xypron.glpk at gmx.de. > >> >> Initially, QEMU would not allow emulating these CPUs running in HYP >> mode (or EL2, for AArch64), but today, it also contains a complete >> implementation of the virtualization extensions themselves. >> >> This means we could be running U-Boot in HYP mode, in which case the >> LPAE long descriptor page table format is the only format that is >> supported. If we are not running in HYP mode, we can use either. >> >> So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we >> get the best support for running with the MMU and caches enabled at >> any privilege level. >> >> Signed-off-by: Ard Biesheuvel <ardb at kernel.org> You missed to CC the maintainer of QEMU ARM 'VIRT' BOARD. - We have scripts/get_maintainer.pl to find the maintainers. Cc: Tuomas Tynkkynen <tuomas.tynkkynen at iki.fi> Best regards Heinrich >> --- >> configs/qemu_arm_defconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig >> index a8473988bd76..75bdce7708c7 100644 >> --- a/configs/qemu_arm_defconfig >> +++ b/configs/qemu_arm_defconfig >> @@ -1,5 +1,6 @@ >> CONFIG_ARM=y >> CONFIG_ARM_SMCCC=y >> +CONFIG_ARMV7_LPAE=y >> CONFIG_ARCH_QEMU=y >> CONFIG_ENV_SIZE=0x40000 >> CONFIG_ENV_SECT_SIZE=0x40000 >>
On Sat, 6 Jun 2020 at 22:49, Heinrich Schuchardt <xypron.glpk at gmx.de> wrote: > > On 6/6/20 10:32 PM, Heinrich Schuchardt wrote: > > On 6/6/20 7:15 PM, Ard Biesheuvel wrote: > >> QEMU's mach-virt machine only supports selecting CPU models that > >> implement the virtualization extensions, and are therefore guaranteed > >> to support LPAE as well. > > > > I wonder why > > qemu-system-arm -machine virt -cpu help > > lists cortex-a9 (which is not LPAE enabled). > > > > But when I try to use it I get > > qemu-system-arm: mach-virt: CPU type cortex-a9-arm-cpu not supported > > This looks like a missing feature in QEMU. > > This is not a missing feature. The virt board uses PSCI for powerdown and reset, and to bring up secondary cores. PSCI requires the HVC instruction, which is only available if the virt extensions are implemented. So emulating CPUs without the virt extensions would require a replacement for PSCI to be implemented as well, which seems rather pointless to me. > > The default CPU for machine=virt is arm,cortex-a15. > > > > Acked-by: Heinrich Schuchardt <xypron.glpk at gmx.de. > > Thanks. > >> > >> Initially, QEMU would not allow emulating these CPUs running in HYP > >> mode (or EL2, for AArch64), but today, it also contains a complete > >> implementation of the virtualization extensions themselves. > >> > >> This means we could be running U-Boot in HYP mode, in which case the > >> LPAE long descriptor page table format is the only format that is > >> supported. If we are not running in HYP mode, we can use either. > >> > >> So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we > >> get the best support for running with the MMU and caches enabled at > >> any privilege level. > >> > >> Signed-off-by: Ard Biesheuvel <ardb at kernel.org> > > You missed to CC the maintainer of QEMU ARM 'VIRT' BOARD. - We have > scripts/get_maintainer.pl to find the maintainers. > > Cc: Tuomas Tynkkynen <tuomas.tynkkynen at iki.fi> > Apologies. I will cc Tuomas for v2.
Am June 7, 2020 8:59:00 AM UTC schrieb Ard Biesheuvel <ardb at kernel.org>: >On Sat, 6 Jun 2020 at 22:49, Heinrich Schuchardt <xypron.glpk at gmx.de> >wrote: >> >> On 6/6/20 10:32 PM, Heinrich Schuchardt wrote: >> > On 6/6/20 7:15 PM, Ard Biesheuvel wrote: >> >> QEMU's mach-virt machine only supports selecting CPU models that >> >> implement the virtualization extensions, and are therefore >guaranteed >> >> to support LPAE as well. >> > >> > I wonder why >> > qemu-system-arm -machine virt -cpu help >> > lists cortex-a9 (which is not LPAE enabled). >> > >> > But when I try to use it I get >> > qemu-system-arm: mach-virt: CPU type cortex-a9-arm-cpu not >supported >> > This looks like a missing feature in QEMU. >> > > >This is not a missing feature. The virt board uses PSCI for powerdown >and reset, and to bring up secondary cores. >PSCI requires the HVC instruction, which is only available if the virt >extensions are implemented. By missing feature I meant -cpu help output should be filtered according to the -machine value if provided. > >So emulating CPUs without the virt extensions would require a >replacement for PSCI to be implemented as well, which seems rather >pointless to me. > >> > The default CPU for machine=virt is arm,cortex-a15. >> > >> > Acked-by: Heinrich Schuchardt <xypron.glpk at gmx.de. >> > > >Thanks. > >> >> >> >> Initially, QEMU would not allow emulating these CPUs running in >HYP >> >> mode (or EL2, for AArch64), but today, it also contains a complete >> >> implementation of the virtualization extensions themselves. >> >> >> >> This means we could be running U-Boot in HYP mode, in which case >the >> >> LPAE long descriptor page table format is the only format that is >> >> supported. If we are not running in HYP mode, we can use either. >> >> >> >> So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that >we >> >> get the best support for running with the MMU and caches enabled >at >> >> any privilege level. >> >> >> >> Signed-off-by: Ard Biesheuvel <ardb at kernel.org> >> >> You missed to CC the maintainer of QEMU ARM 'VIRT' BOARD. - We have >> scripts/get_maintainer.pl to find the maintainers. >> >> Cc: Tuomas Tynkkynen <tuomas.tynkkynen at iki.fi> >> > >Apologies. I will cc Tuomas for v2.
On Sun, 7 Jun 2020 at 13:03, Heinrich Schuchardt <xypron.glpk at gmx.de> wrote: > > Am June 7, 2020 8:59:00 AM UTC schrieb Ard Biesheuvel <ardb at kernel.org>: > >On Sat, 6 Jun 2020 at 22:49, Heinrich Schuchardt <xypron.glpk at gmx.de> > >wrote: > >> > >> On 6/6/20 10:32 PM, Heinrich Schuchardt wrote: > >> > On 6/6/20 7:15 PM, Ard Biesheuvel wrote: > >> >> QEMU's mach-virt machine only supports selecting CPU models that > >> >> implement the virtualization extensions, and are therefore > >guaranteed > >> >> to support LPAE as well. > >> > > >> > I wonder why > >> > qemu-system-arm -machine virt -cpu help > >> > lists cortex-a9 (which is not LPAE enabled). > >> > > >> > But when I try to use it I get > >> > qemu-system-arm: mach-virt: CPU type cortex-a9-arm-cpu not > >supported > >> > This looks like a missing feature in QEMU. > >> > > > > >This is not a missing feature. The virt board uses PSCI for powerdown > >and reset, and to bring up secondary cores. > >PSCI requires the HVC instruction, which is only available if the virt > >extensions are implemented. > > By missing feature I meant -cpu help output should be filtered according to the -machine value if provided. > Ah fair enough. Yes, that would be useful. Unfortunately, ARM does not permit me to contribute to QEMU, so hopefully someone else can take this on.
diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index a8473988bd76..75bdce7708c7 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARM_SMCCC=y +CONFIG_ARMV7_LPAE=y CONFIG_ARCH_QEMU=y CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000
QEMU's mach-virt machine only supports selecting CPU models that implement the virtualization extensions, and are therefore guaranteed to support LPAE as well. Initially, QEMU would not allow emulating these CPUs running in HYP mode (or EL2, for AArch64), but today, it also contains a complete implementation of the virtualization extensions themselves. This means we could be running U-Boot in HYP mode, in which case the LPAE long descriptor page table format is the only format that is supported. If we are not running in HYP mode, we can use either. So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we get the best support for running with the MMU and caches enabled at any privilege level. Signed-off-by: Ard Biesheuvel <ardb at kernel.org> --- configs/qemu_arm_defconfig | 1 + 1 file changed, 1 insertion(+)