| Message ID | 1594370308-30957-4-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Accepted |
| Commit | ea4e9570ebed70c785e0076c65c5490cbd2c947b |
| Headers | show |
| Series | add DM based reset driver for SiFive SoC's | expand |
On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam <sagar.kadam@sifive.com> wrote: > > The resets to DDR and ethernet sub-system are connected to > PRCI device reset control register, these reset signals > are active low and are held low at power-up. Add these reset > producer and consumer details needed by the reset driver. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > --- > arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index afdb4f4..5302677 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 SiFive, Inc */ +#include <dt-bindings/reset/sifive-fu540-prci.h> + / { cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; @@ -59,6 +61,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller at 10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc at 100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800
The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)