| Message ID | 1594370308-30957-2-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Accepted |
| Commit | ef9f65f389de594ac045698004b71df3ab0d0aa7 |
| Headers | show |
| Series | add DM based reset driver for SiFive SoC's | expand |
On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam <sagar.kadam@sifive.com> wrote: > > Add bit indexes for reset signals within the PRCI module > on FU540-C000 SoC. > The DDR and ethernet sub-system's have reset signals > indicated by these reset indexes. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > --- > include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h > Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 0000000..89aa5b6 --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam <sagar.kadam at sifive.com> + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com> --- include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h