| Message ID | 1579513995-1822-3-git-send-email-alex.nemirovsky@cortina-access.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Cortina Access basic DM drivers | expand |
Am 20.01.20 um 10:53 schrieb Alex Nemirovsky: > From: Jason Li <jason.li at cortina-access.com> > > DM_GPIO based GPIO controller driver for CAxxxx SoCs. > This driver support multiple CPU architectures and > Cortina Access SoC platforms. > > Signed-off-by: Jason Li <jason.li at cortina-access.com> > Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com> > --- > > MAINTAINERS | 2 + > drivers/gpio/Kconfig | 8 ++++ > drivers/gpio/Makefile | 1 + > drivers/gpio/cortina_gpio.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 124 insertions(+) > create mode 100644 drivers/gpio/cortina_gpio.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 02b2e11..b7b3359 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -179,6 +179,7 @@ S: Supported > F: board/cortina/common/* > F: board/cortina/common/Kconfig > F: board/cortina/common/armv8/lowlevel_init.S > +F: drivers/gpio/cortina_gpio.c > > ARM/CZ.NIC TURRIS MOX SUPPORT > M: Marek Behun <marek.behun at nic.cz> > @@ -660,6 +661,7 @@ S: Supported > F: board/cortina/common/* > F: board/cortina/common/Kconfig > F: board/cortina/common/mips/* > +F: drivers/gpio/cortina_gpio.c > > MIPS MSCC > M: Gregory CLEMENT <gregory.clement at bootlin.com> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 1de6f52..8a7aa5a 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -59,6 +59,14 @@ config BCM6345_GPIO > help > This driver supports the GPIO banks on BCM6345 SoCs. > > +config CORTINA_GPIO > + bool "Cortina-Access GPIO driver" > + depends on DM_GPIO && CORTINA_PLATFORM > + help > + Enable support for the GPIO controller in Cortina CAxxxx SoCs. > + This driver supports all CPU ISA variants supported by Cortina > + Access CAxxxx SoCs. > + > config DWAPB_GPIO > bool "DWAPB GPIO driver" > depends on DM && DM_GPIO > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 449046b..ceae612 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -17,6 +17,7 @@ endif > obj-$(CONFIG_AT91_GPIO) += at91_gpio.o > obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o > obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o > +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o > obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o > obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o > obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o > diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c > new file mode 100644 > index 0000000..370d475 > --- /dev/null > +++ b/drivers/gpio/cortina_gpio.c > @@ -0,0 +1,113 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright (C) 2020 Cortina-Access > + * Author: Jason Li <Jason.Li at cortina-access.com> > + * > + * GPIO Driver for Cortina Access CAxxxx Line of SoCs > + */ there shouldn't be a blank line after the SPDX identifier. Also the authorship is already recorded within Git and is redundant. > + > +#include <common.h> > +#include <dm.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <linux/compat.h> > +#include <linux/compiler.h> > + > +/* GPIO Register Map */ > +#define CORTINA_GPIO_CFG 0x00 > +#define CORTINA_GPIO_OUT 0x04 > +#define CORTINA_GPIO_IN 0x08 > +#define CORTINA_GPIO_LVL 0x0C > +#define CORTINA_GPIO_EDGE 0x10 > +#define CORTINA_GPIO_BOTHEDGE 0x14 > +#define CORTINA_GPIO_IE 0x18 > +#define CORTINA_GPIO_INT 0x1C > +#define CORTINA_GPIO_STAT 0x20 > + > +struct cortina_gpio_bank { > + void __iomem *base; > +}; > + > +#ifdef CONFIG_DM_GPIO > +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + setbits_32(priv->base, BIT(offset)); > + return 0; > +} > + > +static int > +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + clrbits_32(priv->base, BIT(offset)); > + return 0; > +} > + > +static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); > +} > + > +static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, > + int value) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); > + return 0; > +} > + > +static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + if (readl(priv->base) & BIT(offset)) > + return GPIOF_INPUT; > + else > + return GPIOF_OUTPUT; > +} > + > +static const struct dm_gpio_ops gpio_cortina_ops = { > + .direction_input = ca_gpio_direction_input, > + .direction_output = ca_gpio_direction_output, > + .get_value = ca_gpio_get_value, > + .set_value = ca_gpio_set_value, > + .get_function = ca_gpio_get_function, > +}; > + > +static int ca_gpio_probe(struct udevice *dev) > +{ > + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + priv->base = dev_remap_addr_index(dev, 0); > + if (!priv->base) > + return -EINVAL; > + > + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); > + uc_priv->bank_name = dev->name; > + > + printf("Done Cortina GPIO init\n"); this only blos code size and messes up the boot log. You should remove it or use debug() instead. > + return 0; > +} > + > +static const struct udevice_id ca_gpio_ids[] = { > + {.compatible = "cortina,cortina-gpio"}, > + {} > +}; > + > +U_BOOT_DRIVER(cortina_gpio) = { > + .name = "cortina-gpio", > + .id = UCLASS_GPIO, > + .ops = &gpio_cortina_ops, > + .probe = ca_gpio_probe, > + .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank), > + .of_match = ca_gpio_ids, > +}; > +#endif /* CONFIG_DM_GPIO */ >
Hi Alex, On Mon, 20 Jan 2020 at 02:53, Alex Nemirovsky <Alex.Nemirovsky at cortina-access.com> wrote: > > From: Jason Li <jason.li at cortina-access.com> > > DM_GPIO based GPIO controller driver for CAxxxx SoCs. > This driver support multiple CPU architectures and > Cortina Access SoC platforms. > > Signed-off-by: Jason Li <jason.li at cortina-access.com> > Signed-off-by: Alex Nemirovsky <alex.nemirovsky at cortina-access.com> > --- > > MAINTAINERS | 2 + > drivers/gpio/Kconfig | 8 ++++ > drivers/gpio/Makefile | 1 + > drivers/gpio/cortina_gpio.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 124 insertions(+) > create mode 100644 drivers/gpio/cortina_gpio.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 02b2e11..b7b3359 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -179,6 +179,7 @@ S: Supported > F: board/cortina/common/* > F: board/cortina/common/Kconfig > F: board/cortina/common/armv8/lowlevel_init.S > +F: drivers/gpio/cortina_gpio.c > > ARM/CZ.NIC TURRIS MOX SUPPORT > M: Marek Behun <marek.behun at nic.cz> > @@ -660,6 +661,7 @@ S: Supported > F: board/cortina/common/* > F: board/cortina/common/Kconfig > F: board/cortina/common/mips/* > +F: drivers/gpio/cortina_gpio.c > > MIPS MSCC > M: Gregory CLEMENT <gregory.clement at bootlin.com> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 1de6f52..8a7aa5a 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -59,6 +59,14 @@ config BCM6345_GPIO > help > This driver supports the GPIO banks on BCM6345 SoCs. > > +config CORTINA_GPIO > + bool "Cortina-Access GPIO driver" > + depends on DM_GPIO && CORTINA_PLATFORM > + help > + Enable support for the GPIO controller in Cortina CAxxxx SoCs. > + This driver supports all CPU ISA variants supported by Cortina > + Access CAxxxx SoCs. > + > config DWAPB_GPIO > bool "DWAPB GPIO driver" > depends on DM && DM_GPIO > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 449046b..ceae612 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -17,6 +17,7 @@ endif > obj-$(CONFIG_AT91_GPIO) += at91_gpio.o > obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o > obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o > +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o > obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o > obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o > obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o > diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c > new file mode 100644 > index 0000000..370d475 > --- /dev/null > +++ b/drivers/gpio/cortina_gpio.c > @@ -0,0 +1,113 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright (C) 2020 Cortina-Access > + * Author: Jason Li <Jason.Li at cortina-access.com> > + * > + * GPIO Driver for Cortina Access CAxxxx Line of SoCs > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <linux/compat.h> > +#include <linux/compiler.h> > + > +/* GPIO Register Map */ How about using a struct for this reg? > +#define CORTINA_GPIO_CFG 0x00 > +#define CORTINA_GPIO_OUT 0x04 > +#define CORTINA_GPIO_IN 0x08 > +#define CORTINA_GPIO_LVL 0x0C > +#define CORTINA_GPIO_EDGE 0x10 > +#define CORTINA_GPIO_BOTHEDGE 0x14 > +#define CORTINA_GPIO_IE 0x18 > +#define CORTINA_GPIO_INT 0x1C > +#define CORTINA_GPIO_STAT 0x20 > + > +struct cortina_gpio_bank { > + void __iomem *base; > +}; > + > +#ifdef CONFIG_DM_GPIO Drop this - it will always be true for new boards. > +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + setbits_32(priv->base, BIT(offset)); blank line before return (please fix below too) > + return 0; > +} > + > +static int > +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + clrbits_32(priv->base, BIT(offset)); > + return 0; > +} > + > +static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); > +} > + > +static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, > + int value) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); > + return 0; > +} > + > +static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) > +{ > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + if (readl(priv->base) & BIT(offset)) > + return GPIOF_INPUT; > + else > + return GPIOF_OUTPUT; Does this hardware not support GPIOF_FUNCTION? > +} > + > +static const struct dm_gpio_ops gpio_cortina_ops = { > + .direction_input = ca_gpio_direction_input, > + .direction_output = ca_gpio_direction_output, > + .get_value = ca_gpio_get_value, > + .set_value = ca_gpio_set_value, > + .get_function = ca_gpio_get_function, > +}; > + > +static int ca_gpio_probe(struct udevice *dev) > +{ > + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); > + struct cortina_gpio_bank *priv = dev_get_priv(dev); > + > + priv->base = dev_remap_addr_index(dev, 0); > + if (!priv->base) > + return -EINVAL; > + > + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); > + uc_priv->bank_name = dev->name; > + > + printf("Done Cortina GPIO init\n"); Drop, or change it to debug(). > + return 0; > +} > + > +static const struct udevice_id ca_gpio_ids[] = { > + {.compatible = "cortina,cortina-gpio"}, > + {} > +}; > + > +U_BOOT_DRIVER(cortina_gpio) = { > + .name = "cortina-gpio", > + .id = UCLASS_GPIO, > + .ops = &gpio_cortina_ops, > + .probe = ca_gpio_probe, > + .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank), > + .of_match = ca_gpio_ids, > +}; > +#endif /* CONFIG_DM_GPIO */ > -- > 2.7.4 > Regards, Simon
diff --git a/MAINTAINERS b/MAINTAINERS index 02b2e11..b7b3359 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -179,6 +179,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/armv8/lowlevel_init.S +F: drivers/gpio/cortina_gpio.c ARM/CZ.NIC TURRIS MOX SUPPORT M: Marek Behun <marek.behun at nic.cz> @@ -660,6 +661,7 @@ S: Supported F: board/cortina/common/* F: board/cortina/common/Kconfig F: board/cortina/common/mips/* +F: drivers/gpio/cortina_gpio.c MIPS MSCC M: Gregory CLEMENT <gregory.clement at bootlin.com> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1de6f52..8a7aa5a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -59,6 +59,14 @@ config BCM6345_GPIO help This driver supports the GPIO banks on BCM6345 SoCs. +config CORTINA_GPIO + bool "Cortina-Access GPIO driver" + depends on DM_GPIO && CORTINA_PLATFORM + help + Enable support for the GPIO controller in Cortina CAxxxx SoCs. + This driver supports all CPU ISA variants supported by Cortina + Access CAxxxx SoCs. + config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 449046b..ceae612 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c new file mode 100644 index 0000000..370d475 --- /dev/null +++ b/drivers/gpio/cortina_gpio.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2020 Cortina-Access + * Author: Jason Li <Jason.Li at cortina-access.com> + * + * GPIO Driver for Cortina Access CAxxxx Line of SoCs + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <linux/compiler.h> + +/* GPIO Register Map */ +#define CORTINA_GPIO_CFG 0x00 +#define CORTINA_GPIO_OUT 0x04 +#define CORTINA_GPIO_IN 0x08 +#define CORTINA_GPIO_LVL 0x0C +#define CORTINA_GPIO_EDGE 0x10 +#define CORTINA_GPIO_BOTHEDGE 0x14 +#define CORTINA_GPIO_IE 0x18 +#define CORTINA_GPIO_INT 0x1C +#define CORTINA_GPIO_STAT 0x20 + +struct cortina_gpio_bank { + void __iomem *base; +}; + +#ifdef CONFIG_DM_GPIO +static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base, BIT(offset)); + return 0; +} + +static int +ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + clrbits_32(priv->base, BIT(offset)); + return 0; +} + +static int ca_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset); +} + +static int ca_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset)); + return 0; +} + +static int ca_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + if (readl(priv->base) & BIT(offset)) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops gpio_cortina_ops = { + .direction_input = ca_gpio_direction_input, + .direction_output = ca_gpio_direction_output, + .get_value = ca_gpio_get_value, + .set_value = ca_gpio_set_value, + .get_function = ca_gpio_get_function, +}; + +static int ca_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct cortina_gpio_bank *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; + + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32); + uc_priv->bank_name = dev->name; + + printf("Done Cortina GPIO init\n"); + return 0; +} + +static const struct udevice_id ca_gpio_ids[] = { + {.compatible = "cortina,cortina-gpio"}, + {} +}; + +U_BOOT_DRIVER(cortina_gpio) = { + .name = "cortina-gpio", + .id = UCLASS_GPIO, + .ops = &gpio_cortina_ops, + .probe = ca_gpio_probe, + .priv_auto_alloc_size = sizeof(struct cortina_gpio_bank), + .of_match = ca_gpio_ids, +}; +#endif /* CONFIG_DM_GPIO */