Message ID | 3fbd0ef8418b1b86ea9f9fc0c1c4823b524a8836.1586764831.git.michal.simek@xilinx.com |
---|---|
State | Accepted |
Commit | 783814288b28cc6d63117c15b5755f6396f0c799 |
Headers | show |
Series | arm64: zynqmp: Add label to GPIO lines for boot mode and POR | expand |
po 13. 4. 2020 v 10:00 odes?latel Michal Simek <michal.simek at xilinx.com> napsal: > > From: Saeed Nowshadi <saeed.nowshadi at xilinx.com> > > Add label to GPIO lines controlling boot mode and POR EMIO pins so System > Controller can assert those lines on Versal. > > Signed-off-by: Saeed Nowshadi <saeed.nowshadi at xilinx.com> > Signed-off-by: Michal Simek <michal.simek at xilinx.com> > --- > > arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > index 39b5d7fff9ac..65cf5914945d 100644 > --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts > @@ -162,9 +162,9 @@ > "", "", "", "", "", /* 65 - 69 */ > "", "", "", "", "", /* 70 - 74 */ > "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ > - "", "", /* 78 - 79 */ > - "", "", "", "", "", /* 80 - 84 */ > - "", "", "", "", "", /* 85 -89 */ > + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ > + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ > + "", "", "", "", "", /* 85 - 89 */ > "", "", "", "", "", /* 90 - 94 */ > "", "", "", "", "", /* 95 - 99 */ > "", "", "", "", "", /* 100 - 104 */ > -- > 2.26.0 > Applied. M
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 39b5d7fff9ac..65cf5914945d 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -162,9 +162,9 @@ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */