| Message ID | 20200428062747.8349-5-frank.wang@rock-chips.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Rockchip RK3399 USB3.0 Host support | expand |
Hi Marek, On 2020/4/28 16:27, Marek Vasut wrote: > On 4/28/20 8:27 AM, Frank Wang wrote: >> RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller >> in resetting to hold pipe power state in P2 before initializing the PHY. >> This commit fixed it and added device compatible for rockchip platform. >> >> Signed-off-by: Frank Wang <frank.wang at rock-chips.com> >> --- >> drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ >> 1 file changed, 27 insertions(+), 6 deletions(-) >> >> [...] >> >> + /* >> + * It must hold whole USB3.0 OTG controller in resetting to hold pipe >> + * power state in P2 before initializing TypeC PHY on RK3399 platform. >> + */ >> + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { >> + reset_assert_bulk(&glue->resets); >> + udelay(1); > Reset delay should be handled by the reset controller, no ? This is dwc3's reset phandle linked to CRU on Rockchip platform, however, the reset driver just update the register value, and the timing need to be guaranteed by invoker itself. BR, Frank
Hi Marek, On 2020/4/28 17:21, Marek Vasut wrote: > On 4/28/20 11:05 AM, Frank Wang wrote: >> Hi Marek, >> >> On 2020/4/28 16:27, Marek Vasut wrote: >>> On 4/28/20 8:27 AM, Frank Wang wrote: >>>> RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller >>>> in resetting to hold pipe power state in P2 before initializing the PHY. >>>> This commit fixed it and added device compatible for rockchip platform. >>>> >>>> Signed-off-by: Frank Wang <frank.wang at rock-chips.com> >>>> --- >>>> ? drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ >>>> ? 1 file changed, 27 insertions(+), 6 deletions(-) >>>> >>>> [...] >>>> ? +??? /* >>>> +???? * It must hold whole USB3.0 OTG controller in resetting to hold >>>> pipe >>>> +???? * power state in P2 before initializing TypeC PHY on RK3399 >>>> platform. >>>> +???? */ >>>> +??? if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { >>>> +??????? reset_assert_bulk(&glue->resets); >>>> +??????? udelay(1); >>> Reset delay should be handled by the reset controller, no ? >> This is dwc3's reset phandle linked to CRU on Rockchip platform, >> however, the reset driver just update the register value, and the timing >> need to be guaranteed by invoker itself. > If the reset controller needs a delay after toggling the bit, then it > should add such delay, no ? > That's right.
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index febcfc0f54..0031e8bf44 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -24,6 +24,12 @@ #include <clk.h> #include <usb/xhci.h> +struct dwc3_glue_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + fdt_addr_t regs; +}; + struct dwc3_generic_plat { fdt_addr_t base; u32 maximum_speed; @@ -48,6 +54,7 @@ static int dwc3_generic_probe(struct udevice *dev, int rc; struct dwc3_generic_plat *plat = dev_get_platdata(dev); struct dwc3 *dwc3 = &priv->dwc3; + struct dwc3_glue_data *glue = dev_get_platdata(dev->parent); dwc3->dev = dev; dwc3->maximum_speed = plat->maximum_speed; @@ -56,10 +63,22 @@ static int dwc3_generic_probe(struct udevice *dev, dwc3_of_parse(dwc3); #endif + /* + * It must hold whole USB3.0 OTG controller in resetting to hold pipe + * power state in P2 before initializing TypeC PHY on RK3399 platform. + */ + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { + reset_assert_bulk(&glue->resets); + udelay(1); + } + rc = dwc3_setup_phy(dev, &priv->phys, &priv->num_phys); if (rc) return rc; + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) + reset_deassert_bulk(&glue->resets); + priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE); dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START; @@ -187,12 +206,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = { }; #endif -struct dwc3_glue_data { - struct clk_bulk clks; - struct reset_ctl_bulk resets; - fdt_addr_t regs; -}; - struct dwc3_glue_ops { void (*select_dr_mode)(struct udevice *dev, int index, enum usb_dr_mode mode); @@ -395,6 +408,12 @@ static int dwc3_glue_probe(struct udevice *dev) if (ret) return ret; + if (glue->resets.count < 1) { + ret = dwc3_glue_reset_init(child, glue); + if (ret) + return ret; + } + while (child) { enum usb_dr_mode dr_mode; @@ -425,6 +444,8 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am654-dwc3" }, + { .compatible = "rockchip,rk3328-dwc3" }, + { .compatible = "rockchip,rk3399-dwc3" }, { } };
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform. Signed-off-by: Frank Wang <frank.wang at rock-chips.com> --- drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-)