| Message ID | 20200424165012.31915-9-s.nawrocki@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | USB host support for Raspberry Pi 4 board | expand |
On Fri, 2020-04-24 at 18:50 +0200, Sylwester Nawrocki wrote: > Add PCI Express capability definitions required by the Broadcom > STB PCIe controller driver. > > Reviewed-by: Bin Meng <bmeng.cn at gmail.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com> > --- > Changes since RFC: > - ensure the entries are added in order, sorted by ascending > address values. Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne at suse.de> Regards, Nicolas -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: This is a digitally signed message part URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200427/e4ec48b3/attachment.sig>
diff --git a/include/pci.h b/include/pci.h index 5bf91a4..5307478 100644 --- a/include/pci.h +++ b/include/pci.h @@ -479,11 +479,17 @@ #define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ +#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Include the ID list */