| Message ID | 20200420081727.155029-1-ley.foon.tan@intel.com |
|---|---|
| State | Accepted |
| Commit | b9d1671829b17f78c47f2d0d42a7f59767cdd84b |
| Headers | show |
| Series | arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset | expand |
> -----Original Message----- > From: Tan, Ley Foon <ley.foon.tan at intel.com> > Sent: Monday, April 20, 2020 4:17 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex at denx.de>; Ley Foon Tan <lftan.linux at gmail.com>; > See, Chin Liang <chin.liang.see at intel.com>; Simon Goldschmidt > <simon.k.r.goldschmidt at gmail.com>; Ang, Chee Hong > <chee.hong.ang at intel.com>; Tan, Ley Foon <ley.foon.tan at intel.com> > Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect > CLKMGR_S10_PERPLL_BYPASS offset > > Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. > > Reported-by: Chee Hong Ang <chee.hong.ang at intel.com> > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> > --- > arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h > b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h > index e710aa2f94f0..9d2b3bababe2 100644 > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h > @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg); > #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c > /* Periphpll group */ > #define CLKMGR_S10_PERPLL_EN 0xa4 > -#define CLKMGR_S10_PERPLL_BYPASS 0xac > +#define CLKMGR_S10_PERPLL_BYPASS 0xb0 > #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc > #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0 > #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4 > -- Any comment on this patch? Thanks. Regards Ley Foon
On 4/27/20 9:07 AM, Tan, Ley Foon wrote: > > >> -----Original Message----- >> From: Tan, Ley Foon <ley.foon.tan at intel.com> >> Sent: Monday, April 20, 2020 4:17 PM >> To: u-boot at lists.denx.de >> Cc: Marek Vasut <marex at denx.de>; Ley Foon Tan <lftan.linux at gmail.com>; >> See, Chin Liang <chin.liang.see at intel.com>; Simon Goldschmidt >> <simon.k.r.goldschmidt at gmail.com>; Ang, Chee Hong >> <chee.hong.ang at intel.com>; Tan, Ley Foon <ley.foon.tan at intel.com> >> Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect >> CLKMGR_S10_PERPLL_BYPASS offset >> >> Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. >> >> Reported-by: Chee Hong Ang <chee.hong.ang at intel.com> >> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> >> --- >> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h >> b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h >> index e710aa2f94f0..9d2b3bababe2 100644 >> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h >> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h >> @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg); >> #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c >> /* Periphpll group */ >> #define CLKMGR_S10_PERPLL_EN 0xa4 >> -#define CLKMGR_S10_PERPLL_BYPASS 0xac >> +#define CLKMGR_S10_PERPLL_BYPASS 0xb0 >> #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc >> #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0 >> #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4 >> -- > Any comment on this patch? Applied, thanks.
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index e710aa2f94f0..9d2b3bababe2 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c /* Periphpll group */ #define CLKMGR_S10_PERPLL_EN 0xa4 -#define CLKMGR_S10_PERPLL_BYPASS 0xac +#define CLKMGR_S10_PERPLL_BYPASS 0xb0 #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0 #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it. Reported-by: Chee Hong Ang <chee.hong.ang at intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> --- arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)