| Message ID | 20200423170057.1976-1-jagan@amarulasolutions.com |
|---|---|
| Headers | show |
| Series | riscv: sifive/fu540: Enable SPI-NOR support | expand |
Hello Jagan, > -----Original Message----- > From: Jagan Teki <jagan at amarulasolutions.com> > Sent: Thursday, April 23, 2020 10:31 PM > To: u-boot at lists.denx.de > Cc: Rick Chen <rick at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; > Bhargav Shah <bhargavshah1988 at gmail.com>; Sagar Kadam > <sagar.kadam at sifive.com>; linux-amarula at amarulasolutions.com; Jagan > Teki <jagan at amarulasolutions.com> > Subject: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > This is series v4 for SPI-NOR support on SiFive FU540 platform with HiFive > Unleashed board. > > Here is the previous version changes[1]. > > All patches on top of u-boot-spi/master. > Thanks for posting v4 for spi-nor support. Tested the series above u-boot-spi/master on HiFive Unleashed and was able to verify it for both spi-nor and mmc Additionally just confirmed the opcodes nor is configured with post spi_nor_scan: ====================================================== [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) ================================================================= [SPI MODE in dt with spi-tx-bus-width: <1> ] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) Tested-by: Sagar Kadam <sagar.kadam at sifive.com> Thanks & BR, Sagar Kadam > Changes for v4: > - add spi-mem exec_op > - rebase on master > Changes for v3: > - fixed QPP support > - dropped sf commands log > > [1] > https://patchwork.ozlabs.org/project/uboot/cover/20200420125238.9610-1- > jagan at amarulasolutions.com/ > > Any inputs? > Jagan. > > Jagan Teki (5): > spi: sifive: Add spi-mem exec op > spi: sifive: Fix format register proto field > spi: sifive: Fix QPP transfer > riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi > sifive: fu540: Enable spi-nor flash support > > .../dts/hifive-unleashed-a00-u-boot.dtsi | 11 ++ > board/sifive/fu540/Kconfig | 3 + > drivers/spi/spi-sifive.c | 156 +++++++++++++++--- > 3 files changed, 146 insertions(+), 24 deletions(-) create mode 100644 > arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi > > -- > 2.17.1
On Fri, Apr 24, 2020 at 11:48 PM Sagar Kadam <sagar.kadam at sifive.com> wrote: > > Hello Jagan, > > > -----Original Message----- > > From: Jagan Teki <jagan at amarulasolutions.com> > > Sent: Thursday, April 23, 2020 10:31 PM > > To: u-boot at lists.denx.de > > Cc: Rick Chen <rick at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; > > Bhargav Shah <bhargavshah1988 at gmail.com>; Sagar Kadam > > <sagar.kadam at sifive.com>; linux-amarula at amarulasolutions.com; Jagan > > Teki <jagan at amarulasolutions.com> > > Subject: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > This is series v4 for SPI-NOR support on SiFive FU540 platform with HiFive > > Unleashed board. > > > > Here is the previous version changes[1]. > > > > All patches on top of u-boot-spi/master. > > > > Thanks for posting v4 for spi-nor support. > Tested the series above u-boot-spi/master on HiFive Unleashed and was able to verify it for both spi-nor and mmc > Additionally just confirmed the opcodes nor is configured with post spi_nor_scan: > ====================================================== > [QUAD mode in dt with spi-tx-bus-width: <4>] > pp opcode = 0x34 [QUAD MODE] > read opcode = 0x6c [QUAD MODE] > erase opcode = 0x21 > > SPI-NOR: > 1. erase entire flash: Pass > 2. write entire flash: Pass > 3. read entire flash: Pass > 4. cmp 32MiB read back data: Pass > 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) > ================================================================= > [SPI MODE in dt with spi-tx-bus-width: <1> ] > pp opcode = 0x12 [SPI MODE] > read opcode = 0xc [SPI MODE] > erase opcode = 0x21 > > SPI-NOR: > 1. erase entire flash: Pass > 2. write entire flash: Pass > 3. read entire flash: Pass > 4. cmp 32MiB read back data: Pass > 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity from mmc) > > Tested-by: Sagar Kadam <sagar.kadam at sifive.com> Thanks for detailed testing of Sagar, I will include these use cases on git log,so-that we can find proper info in future. Rick, I would like to pick this via u-boot-spi, let me know if you have any concerns, thanks! Jagan.
Hi Jagan > From: Jagan Teki [mailto:jagan at amarulasolutions.com] > Sent: Saturday, April 25, 2020 7:09 PM > To: Sagar Kadam; Rick Jian-Zhi Chen(???) > Cc: u-boot at lists.denx.de; Bin Meng; Bhargav Shah; linux-amarula at amarulasolutions.com > Subject: Re: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support > > On Fri, Apr 24, 2020 at 11:48 PM Sagar Kadam <sagar.kadam at sifive.com> wrote: > > > > Hello Jagan, > > > > > -----Original Message----- > > > From: Jagan Teki <jagan at amarulasolutions.com> > > > Sent: Thursday, April 23, 2020 10:31 PM > > > To: u-boot at lists.denx.de > > > Cc: Rick Chen <rick at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; > > > Bhargav Shah <bhargavshah1988 at gmail.com>; Sagar Kadam > > > <sagar.kadam at sifive.com>; linux-amarula at amarulasolutions.com; Jagan > > > Teki <jagan at amarulasolutions.com> > > > Subject: [PATCH v4 0/5] riscv: sifive/fu540: Enable SPI-NOR support > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > This is series v4 for SPI-NOR support on SiFive FU540 platform with > > > HiFive Unleashed board. > > > > > > Here is the previous version changes[1]. > > > > > > All patches on top of u-boot-spi/master. > > > > > > > Thanks for posting v4 for spi-nor support. > > Tested the series above u-boot-spi/master on HiFive Unleashed and was > > able to verify it for both spi-nor and mmc Additionally just confirmed the opcodes nor is configured with post spi_nor_scan: > > ====================================================== > > [QUAD mode in dt with spi-tx-bus-width: <4>] > > pp opcode = 0x34 [QUAD MODE] > > read opcode = 0x6c [QUAD MODE] > > erase opcode = 0x21 > > > > SPI-NOR: > > 1. erase entire flash: Pass > > 2. write entire flash: Pass > > 3. read entire flash: Pass > > 4. cmp 32MiB read back data: Pass > > 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity > > from mmc) > > ================================================================= > > [SPI MODE in dt with spi-tx-bus-width: <1> ] > > pp opcode = 0x12 [SPI MODE] > > read opcode = 0xc [SPI MODE] > > erase opcode = 0x21 > > > > SPI-NOR: > > 1. erase entire flash: Pass > > 2. write entire flash: Pass > > 3. read entire flash: Pass > > 4. cmp 32MiB read back data: Pass > > 5. MMC: Booted Linux and dtb from mmc (so as to confirm data integrity > > from mmc) > > > > Tested-by: Sagar Kadam <sagar.kadam at sifive.com> > > Thanks for detailed testing of Sagar, I will include these use cases on git log,so-that we can find proper info in future. > > Rick, > > I would like to pick this via u-boot-spi, let me know if you have any concerns, thanks! > I am OK with it. You can pull it via u-boot-spi. Thanks, Rick > Jagan.