| Message ID | 20200405172230.6.I233a9eabfb1dd95e15ae6c296c03b4cada9c27ca@changeid |
|---|---|
| State | Superseded |
| Headers | show |
| Series | x86: efi: Add a 64-bit coreboot payload | expand |
Hi Simon, On Mon, Apr 6, 2020 at 7:22 AM Simon Glass <sjg at chromium.org> wrote: > > Add a build for running 64-bit U-Boot from coreboot (which is 32-bit). > This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. > > Coreboot boots into SPL and then SPL boots into U-Boot. > > This allows running 64-bit EFI images on x86. > Signed-off-by: Simon Glass <sjg at chromium.org> > --- > > board/coreboot/coreboot/MAINTAINERS | 7 +++++ > configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ > doc/board/coreboot/coreboot.rst | 10 ++++++ > 3 files changed, 65 insertions(+) > create mode 100644 configs/coreboot64_defconfig > > diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS > index 188906b0803..a05673bb0be 100644 > --- a/board/coreboot/coreboot/MAINTAINERS > +++ b/board/coreboot/coreboot/MAINTAINERS > @@ -4,3 +4,10 @@ S: Maintained > F: board/coreboot/coreboot/ > F: include/configs/chromebook_link.h > F: configs/coreboot_defconfig > + > +COREBOOT64 BOARD > +M: Simon Glass <sjg at chromium.org> > +S: Maintained > +F: board/coreboot/coreboot/ > +F: include/configs/chromebook_link.h > +F: configs/coreboot64_defconfig > diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig > new file mode 100644 > index 00000000000..80353b8eb36 > --- /dev/null > +++ b/configs/coreboot64_defconfig > @@ -0,0 +1,48 @@ > +CONFIG_X86=y > +CONFIG_SYS_TEXT_BASE=0x1120000 > +CONFIG_ENV_SIZE=0x1000 > +CONFIG_NR_DRAM_BANKS=8 > +CONFIG_PRE_CON_BUF_ADDR=0x100000 > +CONFIG_X86_RUN_64BIT=y > +CONFIG_VENDOR_COREBOOT=y > +CONFIG_TARGET_COREBOOT=y > +CONFIG_SPL_TEXT_BASE=0x1110000 > +CONFIG_FIT=y > +CONFIG_FIT_SIGNATURE=y > +CONFIG_SHOW_BOOT_PROGRESS=y > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > +CONFIG_PRE_CONSOLE_BUFFER=y > +CONFIG_SYS_CONSOLE_INFO_QUIET=y > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_LAST_STAGE_INIT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_IDE=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_DHCP=y > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_PING=y > +CONFIG_CMD_TIME=y > +CONFIG_CMD_SOUND=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +CONFIG_MAC_PARTITION=y > +# CONFIG_SPL_MAC_PARTITION is not set > +# CONFIG_SPL_DOS_PARTITION is not set > +CONFIG_ISO_PARTITION=y > +CONFIG_EFI_PARTITION=y > +# CONFIG_SPL_EFI_PARTITION is not set > +CONFIG_DEFAULT_DEVICE_TREE="coreboot" > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_REGMAP=y > +CONFIG_SYSCON=y > +# CONFIG_PCI_PNP is not set > +CONFIG_SOUND=y > +CONFIG_SOUND_I8254=y > +CONFIG_CONSOLE_SCROLL_LINES=5 > diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst > index fd974229eb4..9c44c025a48 100644 > --- a/doc/board/coreboot/coreboot.rst > +++ b/doc/board/coreboot/coreboot.rst > @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: > At present it seems that for Minnowboard Max, coreboot does not pass through > the video information correctly (it always says the resolution is 0x0). This > works correctly for link though. > + > +64-bit U-Boot > +------------- > + > +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This > +produces an image which can be booted from coreboot (32-bit). Internally it > +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It > +can be useful for running UEFI applications, for example. > + > +This has only been lightly tested. > -- I tested this with QEMU, but it reboots at U-Boot proper: $ qemu-system-x86_64 -nographic -m 2G -bios coreboot.rom Jumping to boot code at 01110000(7ffd5000) U-Boot SPL 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) CPU: x86_64, vendor AMD, device 663h Trying to boot from SPI Jumping to 64-bit U-Boot: Note many features are missing U-Boot 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) CPU: x86_64, vendor <invalid cpu vendor>, device 0h DRAM: 2 GiB coreboot-4.8.1-dirty Wed May 16 19:00:17 UTC 2018 romstage starting... CBMEM: Regards, Bin Regards, Bin
Hi Bin, On Thu, 23 Apr 2020 at 03:29, Bin Meng <bmeng.cn at gmail.com> wrote: > > Hi Simon, > > On Mon, Apr 6, 2020 at 7:22 AM Simon Glass <sjg at chromium.org> wrote: > > > > Add a build for running 64-bit U-Boot from coreboot (which is 32-bit). > > This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. > > > > Coreboot boots into SPL and then SPL boots into U-Boot. > > > > This allows running 64-bit EFI images on x86. > > Signed-off-by: Simon Glass <sjg at chromium.org> > > --- > > > > board/coreboot/coreboot/MAINTAINERS | 7 +++++ > > configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ > > doc/board/coreboot/coreboot.rst | 10 ++++++ > > 3 files changed, 65 insertions(+) > > create mode 100644 configs/coreboot64_defconfig > > > > diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS > > index 188906b0803..a05673bb0be 100644 > > --- a/board/coreboot/coreboot/MAINTAINERS > > +++ b/board/coreboot/coreboot/MAINTAINERS > > @@ -4,3 +4,10 @@ S: Maintained > > F: board/coreboot/coreboot/ > > F: include/configs/chromebook_link.h > > F: configs/coreboot_defconfig > > + > > +COREBOOT64 BOARD > > +M: Simon Glass <sjg at chromium.org> > > +S: Maintained > > +F: board/coreboot/coreboot/ > > +F: include/configs/chromebook_link.h > > +F: configs/coreboot64_defconfig > > diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig > > new file mode 100644 > > index 00000000000..80353b8eb36 > > --- /dev/null > > +++ b/configs/coreboot64_defconfig > > @@ -0,0 +1,48 @@ > > +CONFIG_X86=y > > +CONFIG_SYS_TEXT_BASE=0x1120000 > > +CONFIG_ENV_SIZE=0x1000 > > +CONFIG_NR_DRAM_BANKS=8 > > +CONFIG_PRE_CON_BUF_ADDR=0x100000 > > +CONFIG_X86_RUN_64BIT=y > > +CONFIG_VENDOR_COREBOOT=y > > +CONFIG_TARGET_COREBOOT=y > > +CONFIG_SPL_TEXT_BASE=0x1110000 > > +CONFIG_FIT=y > > +CONFIG_FIT_SIGNATURE=y > > +CONFIG_SHOW_BOOT_PROGRESS=y > > +CONFIG_USE_BOOTARGS=y > > +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > > +CONFIG_PRE_CONSOLE_BUFFER=y > > +CONFIG_SYS_CONSOLE_INFO_QUIET=y > > +CONFIG_DISPLAY_BOARDINFO_LATE=y > > +CONFIG_LAST_STAGE_INIT=y > > +CONFIG_HUSH_PARSER=y > > +CONFIG_CMD_IDE=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_PART=y > > +CONFIG_CMD_USB=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_CMD_DHCP=y > > +# CONFIG_CMD_NFS is not set > > +CONFIG_CMD_PING=y > > +CONFIG_CMD_TIME=y > > +CONFIG_CMD_SOUND=y > > +CONFIG_CMD_EXT2=y > > +CONFIG_CMD_EXT4=y > > +CONFIG_CMD_EXT4_WRITE=y > > +CONFIG_CMD_FAT=y > > +CONFIG_CMD_FS_GENERIC=y > > +CONFIG_MAC_PARTITION=y > > +# CONFIG_SPL_MAC_PARTITION is not set > > +# CONFIG_SPL_DOS_PARTITION is not set > > +CONFIG_ISO_PARTITION=y > > +CONFIG_EFI_PARTITION=y > > +# CONFIG_SPL_EFI_PARTITION is not set > > +CONFIG_DEFAULT_DEVICE_TREE="coreboot" > > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > +CONFIG_REGMAP=y > > +CONFIG_SYSCON=y > > +# CONFIG_PCI_PNP is not set > > +CONFIG_SOUND=y > > +CONFIG_SOUND_I8254=y > > +CONFIG_CONSOLE_SCROLL_LINES=5 > > diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst > > index fd974229eb4..9c44c025a48 100644 > > --- a/doc/board/coreboot/coreboot.rst > > +++ b/doc/board/coreboot/coreboot.rst > > @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: > > At present it seems that for Minnowboard Max, coreboot does not pass through > > the video information correctly (it always says the resolution is 0x0). This > > works correctly for link though. > > + > > +64-bit U-Boot > > +------------- > > + > > +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This > > +produces an image which can be booted from coreboot (32-bit). Internally it > > +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It > > +can be useful for running UEFI applications, for example. > > + > > +This has only been lightly tested. > > -- > > I tested this with QEMU, but it reboots at U-Boot proper: > > $ qemu-system-x86_64 -nographic -m 2G -bios coreboot.rom > > Jumping to boot code at 01110000(7ffd5000) > > U-Boot SPL 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) > CPU: x86_64, vendor AMD, device 663h > Trying to boot from SPI > Jumping to 64-bit U-Boot: Note many features are missing > > U-Boot 2020.04-00376-g785560e (Apr 23 2020 - 15:50:17 +0800) > > CPU: x86_64, vendor <invalid cpu vendor>, device 0h > DRAM: 2 GiB > > coreboot-4.8.1-dirty Wed May 16 19:00:17 UTC 2018 romstage starting... > CBMEM: > I can't repeat this. My full log is below: $ cbfstool coreboot.rom remove -n fallback/payload $ cbfstool coreboot.rom add-flat-binary -n fallback/payload -f /tmp/b/coreboot64/u-boot-x86-with-spl.bin -c lzma -l 0x1110000 -e 0x1110000 $ qemu-system-x86_64 --nographic -m 2G -bios coreboot.rom (process:24926): GLib-WARNING **: 13:17:13.409: ../../../../glib/gmem.c:489: custom memory allocation vtable not supported coreboot-4.11-2345-gd6f7ec5f44 Sun Apr 26 08:01:17 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xfff00000 size = 0x100000 #areas = 3 FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 389c BS: bootblock times (exec / console): total (unknown) / 1 ms coreboot-4.11-2345-gd6f7ec5f44 Sun Apr 26 08:01:17 UTC 2020 romstage starting (log level: 7)... QEMU: firmware config interface detected Firmware config version id: 1 CBMEM: IMD: root @ 0x7ffff000 254 entries. IMD: root @ 0x7fffec00 62 entries. MTRR Range: Start=fff00000 End=0 (Size 100000) FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset fd40 size 3e5c Decompressing stage fallback/postcar @ 0x7ffd3fc0 (32560 bytes) Loading module at 0x7ffd4000 with entry 0x7ffd4000. filesize: 0x3c10 memsize: 0x7ef0 Processing 124 relocs. Offset value of 0x7dfd4000 BS: romstage times (exec / console): total (unknown) / 2 ms coreboot-4.11-2345-gd6f7ec5f44 Sun Apr 26 08:01:17 UTC 2020 postcar starting (log level: 7)... FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3980 size c064 Decompressing stage fallback/ramstage @ 0x7ffaffc0 (140840 bytes) Loading module at 0x7ffb0000 with entry 0x7ffb0000. filesize: 0x17eb8 memsize: 0x225e8 Processing 1499 relocs. Offset value of 0x7f1b0000 BS: postcar times (exec / console): total (unknown) / 2 ms coreboot-4.11-2345-gd6f7ec5f44 Sun Apr 26 08:01:17 UTC 2020 ramstage starting (log level: 7)... Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected Firmware config version id: 1 QEMU: max_cpus is 1 CPU: APIC: 00 enabled scan_bus: bus CPU_CLUSTER: 0 finished in 0 msecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1234/1111] enabled PCI: 00:03.0 [8086/100e] enabled PCI: 00:01.0 scanning... scan_bus: bus PCI: 00:01.0 finished in 0 msecs PCI: 00:01.3 scanning... scan_bus: bus PCI: 00:01.3 finished in 0 msecs scan_bus: bus DOMAIN: 0000 finished in 1 msecs scan_bus: bus Root Device finished in 2 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 2 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... QEMU: e820/ram: 0x00000000 + 0x80000000 QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] Done reading resources. Setting resources... PCI: 00:01.1 20 <- [0x0000005840 - 0x000000584f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 prefmem PCI: 00:02.0 18 <- [0x00fe070000 - 0x00fe070fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe060000 - 0x00fe06ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x00fe040000 - 0x00fe05ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000005800 - 0x000000583f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x00fe000000 - 0x00fe03ffff] size 0x00040000 gran 0x12 romem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 2 / 3 ms Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 1 / 0 ms Initializing devices... CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device 663 CPU: family 06, model 06, stepping 03 Setting up local APIC... apic_id: 0x00 done. CPU #0 initialized CPU_CLUSTER: 0 init finished in 0 msecs PCI: 00:00.0 init Assigning IRQ 10 to PCI: 00:01.3 Assigning IRQ 11 to PCI: 00:03.0 PCI: 00:00.0 init finished in 1 msecs PCI: 00:01.0 init RTC Init PCI: 00:01.0 init finished in 0 msecs PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:01.1 init finished in 0 msecs PCI: 00:02.0 init PCI: 00:02.0 init finished in 8 msecs PCI: 00:03.0 init PCI: 00:03.0 init finished in 0 msecs Devices initialized BS: BS_DEV_INIT run times (exec / console): 11 / 2 ms Finalize devices... Devices finalized Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x7ffa6000... done. PIRQ table: 128 bytes. QEMU: found ACPI tables in fw_cfg. QEMU: loading "etc/acpi/rsdp" to 0x7ff82000 (len 36) QEMU: loading "etc/acpi/tables" to 0x7ff82040 (len 131072) QEMU: loaded ACPI tables from fw_cfg. Looking on 0x7ff82000 for valid checksum Checksum 1 passed Checksum 2 passed all OK ACPI: * SSDT Found 1 CPU(s). ACPI: added table 5/32, length now 56 ACPI tables: 131136 bytes. smbios_write_tables: 7ff81000 SMBIOS: Unknown CPU DOMAIN: 0000 (QEMU Northbridge i440fx) QEMU: found smbios tables in fw_cfg (len 320). QEMU: coreboot type0 table found at 0x7ff81020. QEMU: loading smbios tables to 0x7ff81065 SMBIOS tables: 421 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum fe4 Writing coreboot table at 0x7ffa7000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007ff80fff: RAM 4. 000000007ff81000-000000007ffaffff: CONFIGURATION TABLES 5. 000000007ffb0000-000000007ffd2fff: RAMSTAGE 6. 000000007ffd3000-000000007fffffff: CONFIGURATION TABLES 7. 00000000ff800000-00000000ffffffff: RESERVED FMAP: area COREBOOT found @ 200 (1048064 bytes) Wrote coreboot table at: 0x7ffa7000, 0x2a0 bytes, checksum df46 coreboot table: 696 bytes. IMD ROOT 0. 0x7ffff000 0x00001000 IMD SMALL 1. 0x7fffe000 0x00001000 CONSOLE 2. 0x7ffde000 0x00020000 TIME STAMP 3. 0x7ffdd000 0x00000910 ROMSTG STCK 4. 0x7ffdc000 0x00001000 AFTER CAR 5. 0x7ffd3000 0x00009000 RAMSTAGE 6. 0x7ffaf000 0x00024000 COREBOOT 7. 0x7ffa7000 0x00008000 IRQ TABLE 8. 0x7ffa6000 0x00001000 ACPI 9. 0x7ff82000 0x00024000 SMBIOS 10. 0x7ff81000 0x00000800 IMD small region: IMD ROOT 0. 0x7fffec00 0x00000400 FMAP 1. 0x7fffeb40 0x000000b6 BS: BS_WRITE_TABLES run times (exec / console): 26 / 5 ms FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 14c00 size 3fa34 Checking segment from ROM address 0xfff14e38 Checking segment from ROM address 0xfff14e54 Loading segment from ROM address 0xfff14e38 code (compression=1) New segment dstaddr 0x01110000 memsize 0x9547b srcaddr 0xfff14e70 filesize 0x3f9fc Loading Segment: addr: 0x01110000 memsz: 0x000000000009547b filesz: 0x000000000003f9fc using LZMA Loading segment from ROM address 0xfff14e54 Entry Point 0x01110000 BS: BS_PAYLOAD_LOAD run times (exec / console): 102 / 1 ms Jumping to boot code at 0x01110000(0x7ffa7000) U-Boot SPL 2020.04-00113-g47a225c571e (Apr 26 2020 - 10:29:50 -0600) CPU: x86_64, vendor AMD, device 663h Trying to boot from SPI Jumping to 64-bit U-Boot: Note many features are missing U-Boot 2020.04-00113-g47a225c571e (Apr 26 2020 - 10:29:50 -0600) CPU: x86_64, vendor <invalid cpu vendor>, device 0h DRAM: 2 GiB MMC: Video: No video mode configured in coreboot! Video: No video mode configured in coreboot! Model: coreboot x86 payload Net: e1000: 52:54:00:12:34:56 Warning: e1000#0 using MAC address from ROM eth0: e1000#0 No working controllers found Finalizing coreboot Hit any key to stop autoboot: 0 Error: Invalid Boot Flag (found 0x0000, expected 0xaa55) ## Kernel loading failed ... zboot - Boot bzImage Usage: zboot [addr] [size] [initrd addr] [initrd size] addr - The optional starting address of the bzimage. If not set it defaults to the environment variable "fileaddr". size - The optional size of the bzimage. Defaults to zero. initrd addr - The address of the initrd image to use, if any. initrd size - The size of the initrd image to use, if any. => QEMU: Terminated Regards, Simon
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 188906b0803..a05673bb0be 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/coreboot/coreboot/ F: include/configs/chromebook_link.h F: configs/coreboot_defconfig + +COREBOOT64 BOARD +M: Simon Glass <sjg at chromium.org> +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot64_defconfig diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig new file mode 100644 index 00000000000..80353b8eb36 --- /dev/null +++ b/configs/coreboot64_defconfig @@ -0,0 +1,48 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1120000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_PRE_CON_BUF_ADDR=0x100000 +CONFIG_X86_RUN_64BIT=y +CONFIG_VENDOR_COREBOOT=y +CONFIG_TARGET_COREBOOT=y +CONFIG_SPL_TEXT_BASE=0x1110000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="coreboot" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_PCI_PNP is not set +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index fd974229eb4..9c44c025a48 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot: At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. + +64-bit U-Boot +------------- + +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This +produces an image which can be booted from coreboot (32-bit). Internally it +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It +can be useful for running UEFI applications, for example. + +This has only been lightly tested.
Add a build for running 64-bit U-Boot from coreboot (which is 32-bit). This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. Coreboot boots into SPL and then SPL boots into U-Boot. This allows running 64-bit EFI images on x86. Signed-off-by: Simon Glass <sjg at chromium.org> --- board/coreboot/coreboot/MAINTAINERS | 7 +++++ configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++ doc/board/coreboot/coreboot.rst | 10 ++++++ 3 files changed, 65 insertions(+) create mode 100644 configs/coreboot64_defconfig