diff mbox series

[06/27] dm: powerpc: P1020: add i2c DM support

Message ID 20200412085428.27519-6-biwen.li@oss.nxp.com
State New
Headers show
Series [01/27] rtc: ds1337: Add driver model support | expand

Commit Message

Biwen Li (OSS) April 12, 2020, 8:54 a.m. UTC 
From: Biwen Li <biwen.li at nxp.com>

This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li <biwen.li at nxp.com>
---
 arch/powerpc/dts/p1020-post.dtsi            |  2 ++
 arch/powerpc/dts/p1020.dtsi                 |  2 +-
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24 ++++++++++++++++++++-
 include/configs/P1022DS.h                   |  5 ++++-
 include/configs/p1_p2_rdb_pc.h              |  7 ++++++
 5 files changed, 37 insertions(+), 3 deletions(-)

Comments

Priyanka Jain (OSS) April 16, 2020, 8:30 a.m. UTC | #1 
>-----Original Message-----
>From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya at nxp.com>; Priyanka Jain
><priyanka.jain at nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang at nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1 at nxp.com>;
>Rajesh Bhagat <rajesh.bhagat at nxp.com>; Ruchika Gupta
><ruchika.gupta at nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie at nxp.com>; Jiafei Pan <jiafei.pan at nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou at nxp.com>; Biwen Li
><biwen.li at nxp.com>
>Subject: [PATCH 06/27] dm: powerpc: P1020: add i2c DM support
>
>From: Biwen Li <biwen.li at nxp.com>
>
>This supports i2c DM for SoC P1020
>
>Signed-off-by: Biwen Li <biwen.li at nxp.com>
>---
> arch/powerpc/dts/p1020-post.dtsi            |  2 ++
> arch/powerpc/dts/p1020.dtsi                 |  2 +-
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24
>++++++++++++++++++++-
> include/configs/P1022DS.h                   |  5 ++++-
> include/configs/p1_p2_rdb_pc.h              |  7 ++++++
> 5 files changed, 37 insertions(+), 3 deletions(-)
>
>diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-
>post.dtsi
>index 1c77702f01..1dce8e86e9 100644
>--- a/arch/powerpc/dts/p1020-post.dtsi
>+++ b/arch/powerpc/dts/p1020-post.dtsi
>@@ -44,6 +44,8 @@
> 		clock-frequency = <0>;
> 	};
>
>+	/include/ "pq3-i2c-0.dtsi"
>+	/include/ "pq3-i2c-1.dtsi"
> };
>
> /* PCIe controller base address 0x9000 */ diff --git
>a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi index
>ee2b6f4945..facc251953 100644
>--- a/arch/powerpc/dts/p1020.dtsi
>+++ b/arch/powerpc/dts/p1020.dtsi
>@@ -3,7 +3,7 @@
>  * P1020 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2013 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>index 71fca8ca1e..f668d7efb1 100644
>--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> #include <common.h>
>@@ -227,6 +228,7 @@ int checkboard(void)
> 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> 	u8 in, out, io_config, val;
>+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n",
>CONFIG_BOARDNAME,
> 		in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7
>+236,26 @@ int checkboard(void)
> 		in_8(&cpld_data->pcba_rev) & 0x0F);
>
> 	/* Initialize i2c early for rom_loc and flash bank information */
>-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
>+	#if defined(CONFIG_DM_I2C)
>+	struct udevice *dev;
>+	int ret;
>+
>+	ret = i2c_get_chip_for_busnum(bus_num,
>CONFIG_SYS_I2C_PCA9557_ADDR,
>+				      1, &dev);
>+	if (ret) {
>+		printf("%s: Cannot find udev for a bus %d\n", __func__,
>+		       bus_num);
>+		return -ENXIO;
>+	}
>+
>+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
>+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
>+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
>+		printf("Error reading i2c boot information!\n");
>+		return 0; /* Don't want to hang() on this error */
>+	}
>+	#else /* Non DM I2C support - will be removed */
>+	i2c_set_bus_num(bus_num);
>
> 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
>@@ -242,6 +263,7 @@ int checkboard(void)
> 		printf("Error reading i2c boot information!\n");
> 		return 0; /* Don't want to hang() on this error */
> 	}
>+	#endif
>
> 	val = (in & io_config) | (out & (~io_config));
>
>diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index
>5cc2e06979..f1d77c8e1c 100644
>--- a/include/configs/P1022DS.h
>+++ b/include/configs/P1022DS.h
>@@ -359,16 +359,19 @@
> #endif
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
>+#endif
>+
> #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
>
>+#define CONFIG_SYS_I2C_FSL
> /*
>  * I2C2 EEPROM
>  */
>diff --git a/include/configs/p1_p2_rdb_pc.h
>b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce..7089b69bf3 100644
>--- a/include/configs/p1_p2_rdb_pc.h
>+++ b/include/configs/p1_p2_rdb_pc.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2010-2011 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -546,6 +547,12 @@
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
>+
>+#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
>bank */
>
>--
>2.17.1
Reviewed-by: Priyanka Jain <priyanka.jain at nxp.com>
Priyanka Jain (OSS) April 16, 2020, 8:44 a.m. UTC | #2 
>-----Original Message-----
>From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya at nxp.com>; Priyanka Jain
><priyanka.jain at nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang at nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1 at nxp.com>;
>Rajesh Bhagat <rajesh.bhagat at nxp.com>; Ruchika Gupta
><ruchika.gupta at nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie at nxp.com>; Jiafei Pan <jiafei.pan at nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou at nxp.com>; Biwen Li
><biwen.li at nxp.com>
>Subject: [PATCH 06/27] dm: powerpc: P1020: add i2c DM support
>
>From: Biwen Li <biwen.li at nxp.com>
>
>This supports i2c DM for SoC P1020
>
>Signed-off-by: Biwen Li <biwen.li at nxp.com>
>---
> arch/powerpc/dts/p1020-post.dtsi            |  2 ++
> arch/powerpc/dts/p1020.dtsi                 |  2 +-
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24
>++++++++++++++++++++-
> include/configs/P1022DS.h                   |  5 ++++-
> include/configs/p1_p2_rdb_pc.h              |  7 ++++++
> 5 files changed, 37 insertions(+), 3 deletions(-)
>
>diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-
>post.dtsi
>index 1c77702f01..1dce8e86e9 100644
>--- a/arch/powerpc/dts/p1020-post.dtsi
>+++ b/arch/powerpc/dts/p1020-post.dtsi
>@@ -44,6 +44,8 @@
> 		clock-frequency = <0>;
> 	};
>
>+	/include/ "pq3-i2c-0.dtsi"
>+	/include/ "pq3-i2c-1.dtsi"
> };
>
> /* PCIe controller base address 0x9000 */ diff --git
>a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi index
>ee2b6f4945..facc251953 100644
>--- a/arch/powerpc/dts/p1020.dtsi
>+++ b/arch/powerpc/dts/p1020.dtsi
>@@ -3,7 +3,7 @@
>  * P1020 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2013 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>index 71fca8ca1e..f668d7efb1 100644
>--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> #include <common.h>
>@@ -227,6 +228,7 @@ int checkboard(void)
> 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> 	u8 in, out, io_config, val;
>+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n",
>CONFIG_BOARDNAME,
> 		in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7
>+236,26 @@ int checkboard(void)
> 		in_8(&cpld_data->pcba_rev) & 0x0F);
>
> 	/* Initialize i2c early for rom_loc and flash bank information */
>-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
>+	#if defined(CONFIG_DM_I2C)
>+	struct udevice *dev;
>+	int ret;
>+
>+	ret = i2c_get_chip_for_busnum(bus_num,
>CONFIG_SYS_I2C_PCA9557_ADDR,
>+				      1, &dev);
>+	if (ret) {
>+		printf("%s: Cannot find udev for a bus %d\n", __func__,
>+		       bus_num);
>+		return -ENXIO;
>+	}
>+
>+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
>+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
>+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
>+		printf("Error reading i2c boot information!\n");
>+		return 0; /* Don't want to hang() on this error */
>+	}
>+	#else /* Non DM I2C support - will be removed */
>+	i2c_set_bus_num(bus_num);
>
> 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
>@@ -242,6 +263,7 @@ int checkboard(void)
> 		printf("Error reading i2c boot information!\n");
> 		return 0; /* Don't want to hang() on this error */
> 	}
>+	#endif
>
> 	val = (in & io_config) | (out & (~io_config));
>
>diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index
>5cc2e06979..f1d77c8e1c 100644
>--- a/include/configs/P1022DS.h
>+++ b/include/configs/P1022DS.h
>@@ -359,16 +359,19 @@
> #endif
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
>+#endif
>+
> #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
>
>+#define CONFIG_SYS_I2C_FSL
> /*
>  * I2C2 EEPROM
>  */
>diff --git a/include/configs/p1_p2_rdb_pc.h
>b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce..7089b69bf3 100644
>--- a/include/configs/p1_p2_rdb_pc.h
>+++ b/include/configs/p1_p2_rdb_pc.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2010-2011 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -546,6 +547,12 @@
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
Biwen,

One thing I missed earlier, where is corresponding #ifdef

Regards
Priyanka
>+
>+#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
>bank */
>
>--
>2.17.1
Biwen Li April 16, 2020, 8:52 a.m. UTC | #3 
> >--- a/include/configs/p1_p2_rdb_pc.h
> >+++ b/include/configs/p1_p2_rdb_pc.h
> >@@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >  * Copyright 2010-2011 Freescale Semiconductor, Inc.
> >+ * Copyright 2020 NXP
> >  */
> >
> > /*
> >@@ -546,6 +547,12 @@
> > #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> > #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
> >+#else
> >+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> >+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
> >+#endif
> Biwen,
> 
> One thing I missed earlier, where is corresponding #ifdef
Yeah, I missed #ifndef,
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
#endif

#define CONFIG_SYS_I2C_FSL
> 
> Regards
> Priyanka
> >+
> >+#define CONFIG_SYS_I2C_FSL
> > #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> > #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
> >bank */
> >
> >--
> >2.17.1
diff mbox series

Patch

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1c77702f01..1dce8e86e9 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,6 +44,8 @@ 
 		clock-frequency = <0>;
 	};
 
+	/include/ "pq3-i2c-0.dtsi"
+	/include/ "pq3-i2c-1.dtsi"
 };
 
 /* PCIe controller base address 0x9000 */
diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi
index ee2b6f4945..facc251953 100644
--- a/arch/powerpc/dts/p1020.dtsi
+++ b/arch/powerpc/dts/p1020.dtsi
@@ -3,7 +3,7 @@ 
  * P1020 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 71fca8ca1e..f668d7efb1 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -1,6 +1,7 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -227,6 +228,7 @@  int checkboard(void)
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, io_config, val;
+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
@@ -234,7 +236,26 @@  int checkboard(void)
 		in_8(&cpld_data->pcba_rev) & 0x0F);
 
 	/* Initialize i2c early for rom_loc and flash bank information */
-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+	#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+
+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+	#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
 
 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
@@ -242,6 +263,7 @@  int checkboard(void)
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
+	#endif
 
 	val = (in & io_config) | (out & (~io_config));
 
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 5cc2e06979..f1d77c8e1c 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -359,16 +359,19 @@ 
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#endif
+
 #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
 
+#define CONFIG_SYS_I2C_FSL
 /*
  * I2C2 EEPROM
  */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index c42f1a9fce..7089b69bf3 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -1,6 +1,7 @@ 
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -546,6 +547,12 @@ 
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+
+#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */