Message ID | 1582115146-28658-16-git-send-email-chee.hong.ang@intel.com |
---|---|
State | Superseded |
Headers | show |
Series | Enable ARM Trusted Firmware for U-Boot | expand |
> From: Chee Hong Ang <chee.hong.ang at intel.com> > > Allow MAC driver to access System Manager's EMAC control registers in non- > secure mode. > > Signed-off-by: Chee Hong Ang <chee.hong.ang at intel.com> > --- > drivers/net/dwmac_socfpga.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index > e93561d..293c660 100644 > --- a/drivers/net/dwmac_socfpga.c > +++ b/drivers/net/dwmac_socfpga.c > @@ -17,6 +17,7 @@ > #include <dm/device_compat.h> > #include <linux/err.h> > > +#include <asm/arch/secure_reg_helper.h> > #include <asm/arch/system_manager.h> > > struct dwmac_socfpga_platdata { > @@ -98,8 +99,8 @@ static int dwmac_socfpga_probe(struct udevice *dev) > reset_assert_bulk(&reset_bulk); > > modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata- > >reg_shift; > - clrsetbits_le32(pdata->phy_intf, modemask, > - modereg << pdata->reg_shift); > + socfpga_secure_reg_update32((phys_addr_t)pdata->phy_intf, > modemask, > + modereg << pdata->reg_shift); > > reset_release_bulk(&reset_bulk); > > -- > 2.7.4 This MAC driver need to access System Manager's EMAC control register (secure zone) to configure the PHY interface (GMII/RGMII/RMII). This should be part of this MAC driver as well. I will add/define a high-level API in ATF to be used by this MAC driver from non-secure world (EL2). This high-level API (SMC/PSCI calls) will be properly documented in 'include/linux/intel-smc.h'
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index e93561d..293c660 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -17,6 +17,7 @@ #include <dm/device_compat.h> #include <linux/err.h> +#include <asm/arch/secure_reg_helper.h> #include <asm/arch/system_manager.h> struct dwmac_socfpga_platdata { @@ -98,8 +99,8 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_assert_bulk(&reset_bulk); modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; - clrsetbits_le32(pdata->phy_intf, modemask, - modereg << pdata->reg_shift); + socfpga_secure_reg_update32((phys_addr_t)pdata->phy_intf, modemask, + modereg << pdata->reg_shift); reset_release_bulk(&reset_bulk);