diff mbox series

imx8mm/mn: Add missing root clock entry for ARM core clock

Message ID 20200205114527.15113-1-frieder.schrempf@kontron.de
State Accepted
Commit 291e3ab9044f65209043195ca22a97626d3402f7
Headers show
Series imx8mm/mn: Add missing root clock entry for ARM core clock | expand

Commit Message

Frieder Schrempf Feb. 5, 2020, 11:45 a.m. UTC 
From: Frieder Schrempf <frieder.schrempf at kontron.de>

The current implementation in arch/arm/mach-imx/cpu.c uses non-DM
code to retrieve the core clock frequency. As the root clock is not
listed we currently get:

CPU:   Freescale i.MX8MMQ rev1.0 at 0 MHz

Fix this by adding the missing entry, which results in:

CPU:   Freescale i.MX8MMQ rev1.0 at 1200 MHz

Signed-off-by: Frieder Schrempf <frieder.schrempf at kontron.de>
---
 arch/arm/mach-imx/imx8m/clock_slice.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Fabio Estevam Feb. 5, 2020, 1:46 p.m. UTC | #1 
Hi Frieder,

On Wed, Feb 5, 2020 at 8:45 AM Schrempf Frieder
<frieder.schrempf at kontron.de> wrote:
>
> From: Frieder Schrempf <frieder.schrempf at kontron.de>
>
> The current implementation in arch/arm/mach-imx/cpu.c uses non-DM
> code to retrieve the core clock frequency. As the root clock is not
> listed we currently get:
>
> CPU:   Freescale i.MX8MMQ rev1.0 at 0 MHz
>
> Fix this by adding the missing entry, which results in:
>
> CPU:   Freescale i.MX8MMQ rev1.0 at 1200 MHz
>
> Signed-off-by: Frieder Schrempf <frieder.schrempf at kontron.de>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam at gmail.com>
diff mbox series

Patch

diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 31925ccaba..8b7a4dad65 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -477,6 +477,11 @@  static struct clk_root_map root_array[] = {
 };
 #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 static struct clk_root_map root_array[] = {
+	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+	},
 	{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
 	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
 	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,