mbox series

[0/6] Add interconnect support to UART, I2C, SPI and QSPI

Message ID 1581946205-27189-1-git-send-email-akashast@codeaurora.org
Headers show
Series Add interconnect support to UART, I2C, SPI and QSPI | expand

Message

Akash Asthana Feb. 17, 2020, 1:29 p.m. UTC
dt-binding patch for UART, I2C and SPI.
 - https://patchwork.kernel.org/patch/11385965/ [Convert QUP bindings
	to YAML and add ICC, pin swap doc]

dt-binding patch for QSPI.
 - https://patchwork.kernel.org/cover/11386003/ [Convert QSPI binding
	to YAML and add interconnect doc]

Akash Asthana (6):
  soc: qcom: geni: Support for ICC voting
  tty: serial: qcom_geni_serial: Add interconnect support
  i2c: i2c-qcom-geni: Add interconnect support
  spi: spi-geni-qcom: Add interconnect support
  spi: spi-qcom-qspi: Add interconnect support
  arm64: dts: sc7180: Add interconnect for QUP and QSPI

 arch/arm64/boot/dts/qcom/sc7180.dtsi  | 199 ++++++++++++++++++++++++++++++++++
 drivers/i2c/busses/i2c-qcom-geni.c    |  84 +++++++++++++-
 drivers/spi/spi-geni-qcom.c           |  65 ++++++++++-
 drivers/spi/spi-qcom-qspi.c           |  38 ++++++-
 drivers/tty/serial/qcom_geni_serial.c |  84 ++++++++++++--
 include/linux/qcom-geni-se.h          |  31 ++++++
 6 files changed, 481 insertions(+), 20 deletions(-)

Comments

Greg KH Feb. 17, 2020, 4 p.m. UTC | #1
On Mon, Feb 17, 2020 at 07:00:01PM +0530, Akash Asthana wrote:
> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++-----
>  1 file changed, 74 insertions(+), 10 deletions(-)

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Bjorn Andersson Feb. 18, 2020, 3:03 a.m. UTC | #2
On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:

> Add necessary enums, macros and structure variables to support ICC BW
> voting from individual SE drivers.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  include/linux/qcom-geni-se.h | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
> index dd46494..b0adbfb 100644
> --- a/include/linux/qcom-geni-se.h
> +++ b/include/linux/qcom-geni-se.h
> @@ -6,6 +6,8 @@
>  #ifndef _LINUX_QCOM_GENI_SE
>  #define _LINUX_QCOM_GENI_SE
>  
> +#include <linux/interconnect.h>
> +
>  /* Transfer mode supported by GENI Serial Engines */
>  enum geni_se_xfer_mode {
>  	GENI_SE_INVALID,
> @@ -22,6 +24,13 @@ enum geni_se_protocol_type {
>  	GENI_SE_I3C,
>  };
>  
> +/* Interconnect paths for GENI */
> +enum geni_se_icc_path {
> +	GENI_TO_CORE,
> +	CPU_TO_GENI,
> +	GENI_TO_DDR
> +};
> +
>  struct geni_wrapper;
>  struct clk;
>  
> @@ -33,6 +42,13 @@ struct clk;
>   * @clk:		Handle to the core serial engine clock
>   * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
>   * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
> + * @icc_path:		Array of interconnect path handles
> + * @avg_bw_core:	Average bus bandwidth value for QUP core 2x clock
> + * @peak_bw_core:	Peak bus bandwidth value for QUP core 2x clock
> + * @avg_bw_cpu:		Average bus bandwidth value for CPU
> + * @peak_bw_cpu:	Peak bus bandwidth value for CPU
> + * @avg_bw_ddr:		Average bus bandwidth value for DDR
> + * @peak_bw_ddr:	Peak bus bandwidth value for DDR
>   */
>  struct geni_se {
>  	void __iomem *base;
> @@ -41,6 +57,13 @@ struct geni_se {
>  	struct clk *clk;
>  	unsigned int num_clk_levels;
>  	unsigned long *clk_perf_tbl;
> +	struct icc_path *icc_path[3];

In all cases you refer to icc_path[IDENIFIER], so just give the three
paths individual members and drop the enum above.

Reards,
Bjorn

> +	unsigned int avg_bw_core;
> +	unsigned int peak_bw_core;
> +	unsigned int avg_bw_cpu;
> +	unsigned int peak_bw_cpu;
> +	unsigned int avg_bw_ddr;
> +	unsigned int peak_bw_ddr;
>  };
>  
>  /* Common SE registers */
> @@ -229,6 +252,14 @@ struct geni_se {
>  #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
>  #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
>  
> +/* Core 2X clock frequency to BCM threshold mapping */
> +#define CORE_2X_19_2_MHZ		960
> +#define CORE_2X_50_MHZ			2500
> +#define CORE_2X_100_MHZ			5000
> +#define CORE_2X_150_MHZ			7500
> +#define CORE_2X_200_MHZ			10000
> +#define CORE_2X_236_MHZ			16383
> +
>  #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
>  
>  u32 geni_se_get_qup_hw_version(struct geni_se *se);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
Bjorn Andersson Feb. 18, 2020, 3:18 a.m. UTC | #3
On Mon 17 Feb 05:30 PST 2020, Akash Asthana wrote:

> Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
> Note:
>  - This patch depends on series https://patchwork.kernel.org/cover/11313817/
>    [Add SC7180 interconnect provider driver]. It won't compile without that.
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
>  1 file changed, 199 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index cc5a94f..04569c9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -352,6 +352,14 @@
>  				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>  				#address-cells = <1>;
>  				#size-cells = <0>;
> +				interconnects = <&qup_virt MASTER_QUP_CORE_0
> +						&qup_virt SLAVE_QUP_CORE_0>,
> +						<&gem_noc MASTER_APPSS_PROC
> +						&config_noc SLAVE_QUP_0>,
> +						<&aggre1_noc MASTER_QUP_0
> +						&mc_virt SLAVE_EBI1>;

Please ignore the 80-char "limit" and write this as:
				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
						<&gem_noc ...>,
						<&aggre1_noc ...>;

Regards,
Bjorn
Matthias Kaehlcke Feb. 18, 2020, 10:47 p.m. UTC | #4
On Mon, Feb 17, 2020 at 07:00:02PM +0530, Akash Asthana wrote:
> Get the interconnect paths for I2C based Serial Engine device
> and vote according to the bus speed of the driver.
> 
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
>  drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++--
>  1 file changed, 80 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
> index 17abf60c..5de10a1 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -163,6 +163,44 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
>  	writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
>  }
>  
> +static int geni_i2c_icc_get(struct geni_se *se)
> +{
> +	if (!se)
> +		return -EINVAL;

check is not needed

> +
> +	se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
> +	if (IS_ERR(se->icc_path[GENI_TO_CORE]))
> +		return PTR_ERR(se->icc_path[GENI_TO_CORE]);
> +
> +	se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
> +	if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;

echoing Bjorn's comments on 'tty: serial: qcom_geni_serial: Add
interconnect support', resetting is not needed since _probe() will
fail.

> +		return PTR_ERR(se->icc_path[CPU_TO_GENI]);
> +	}
> +
> +	se->icc_path[GENI_TO_DDR] = of_icc_get(se->dev, "qup-memory");
> +	if (IS_ERR(se->icc_path[GENI_TO_DDR])) {
> +		icc_put(se->icc_path[GENI_TO_CORE]);
> +		se->icc_path[GENI_TO_CORE] = NULL;

ditto

> +		icc_put(se->icc_path[CPU_TO_GENI]);
> +		se->icc_path[CPU_TO_GENI] = NULL;

ditto

> +		return PTR_ERR(se->icc_path[GENI_TO_DDR]);
> +	}
> +
> +	return 0;
> +}
> +
> +void geni_i2c_icc_put(struct geni_se *se)
> +{
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
> +		icc_put(se->icc_path[i]);
> +		se->icc_path[i] = NULL;

not needed

> +	}
> +}
> +
>  static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
>  {
>  	u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
> @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev)
>  	gi2c->adap.dev.of_node = pdev->dev.of_node;
>  	strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
>  
> +	ret = geni_i2c_icc_get(&gi2c->se);
> +	if (ret)
> +		return ret;
> +	/* Set the bus quota to a reasonable value */
> +	gi2c->se.avg_bw_core = Bps_to_icc(1000);
> +	gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
> +	gi2c->se.avg_bw_cpu = Bps_to_icc(1000);
> +	gi2c->se.peak_bw_cpu = Bps_to_icc(1000);
> +	gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out);
> +	gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out);
> +
> +	/* Vote for core clocks and CPU for register access */
> +	icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core,
> +				gi2c->se.peak_bw_core);
> +	icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu,
> +				gi2c->se.peak_bw_cpu);

error handling needed?
Akash Asthana Feb. 19, 2020, 1:25 p.m. UTC | #5
Hi Bjorn,

>>   	struct clk *clk;
>>   	unsigned int num_clk_levels;
>>   	unsigned long *clk_perf_tbl;
>> +	struct icc_path *icc_path[3];
> In all cases you refer to icc_path[IDENIFIER], so just give the three
> paths individual members and drop the enum above.
>
> Reards,
> Bjorn

Ok

Thanks for reviewing.

Regards,

Akash

>
>> +	unsigned int avg_bw_core;
>> Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
Akash Asthana Feb. 19, 2020, 1:31 p.m. UTC | #6
Hi Matthias,

On 2/19/2020 4:04 AM, Matthias Kaehlcke wrote:
> On Mon, Feb 17, 2020 at 07:00:01PM +0530, Akash Asthana wrote:
>> Get the interconnect paths for Uart based Serial Engine device
>> and vote according to the baud rate requirement of the driver.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> ---
>>
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
>> +	port->se.avg_bw_cpu = Bps_to_icc(1000);
> I guess you mean 'peak_bw_cpu'?

Yes I meant peak_bw_cpu here, i will correct it in next version.

Regards,

Akash
Akash Asthana Feb. 19, 2020, 1:49 p.m. UTC | #7
Hi Bjorn,

>> +				interconnects = <&qup_virt MASTER_QUP_CORE_0
>> +						&qup_virt SLAVE_QUP_CORE_0>,
>> +						<&gem_noc MASTER_APPSS_PROC
>> +						&config_noc SLAVE_QUP_0>,
>> +						<&aggre1_noc MASTER_QUP_0
>> +						&mc_virt SLAVE_EBI1>;
> Please ignore the 80-char "limit" and write this as:
> 				interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
> 						<&gem_noc ...>,
> 						<&aggre1_noc ...>;
>
> Regards,
> Bjorn

ok

Regards,

Akash
Matthias Kaehlcke Feb. 27, 2020, 5:03 p.m. UTC | #8
Hi Amit,

the following include is missing:

#include <dt-bindings/interconnect/qcom,sc7180.h>

It was added in v2 of "arm64: dts: sc7180: Add interconnect provider DT.
nodes", but removed in later versions. v2 had a comment requesting to move
the include one line up, my guess is it got lost while doing that.

On Thu, Feb 27, 2020 at 05:41:03PM +0530, Amit Kucheria wrote:
> Hi Akash,
> 
> 
> On Mon, Feb 17, 2020 at 7:01 PM Akash Asthana <akashast@codeaurora.org> wrote:
> >
> > Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
> >
> > Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> > ---
> > Note:
> >  - This patch depends on series https://patchwork.kernel.org/cover/11313817/
> >    [Add SC7180 interconnect provider driver]. It won't compile without that.
> 
> I've tried picking up v4 of Odelu's series to add the SC7180 but I'm
> still unable to compile this. I see the following error:
> 
> Error: /home/amit/work/sources/worktree-review-pipeline/arch/arm64/boot/dts/qcom/sc7180.dtsi:353.32-33
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[3]: *** [scripts/Makefile.lib:296:
> arch/arm64/boot/dts/qcom/sc7180-idp.dtb] Error 1
> 
> As part of picking up the dependencies, I've pulled the following
> series on top of v5.6-rc2:
> 
> - https://lore.kernel.org/r/1581932974-21654-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1581932212-19469-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1581946205-27189-2-git-send-email-akashast@codeaurora.org
> - https://lore.kernel.org/r/1582646384-1458-2-git-send-email-okukatla@codeaurora.org
> - https://lore.kernel.org/r/20200209183411.17195-2-sibis@codeaurora.org
> 
> What am I missing?
> 
> I've pushed the aggregate branch here for convenience:
> https://git.linaro.org/people/amit.kucheria/kernel.git/log/
> 
> Regards,
> Amit
> 
> >  arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 199 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > index cc5a94f..04569c9 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > @@ -352,6 +352,14 @@
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -365,6 +373,11 @@
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -376,6 +389,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart0_default>;
> >                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -389,6 +407,14 @@
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -402,6 +428,11 @@
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -413,6 +444,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart1_default>;
> >                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -426,6 +462,14 @@
> >                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -437,6 +481,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart2_default>;
> >                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -450,6 +499,14 @@
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -463,6 +520,11 @@
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -474,6 +536,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart3_default>;
> >                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -487,6 +554,14 @@
> >                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -498,6 +573,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart4_default>;
> >                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -511,6 +591,14 @@
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>,
> > +                                               <&aggre1_noc MASTER_QUP_0
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -524,6 +612,11 @@
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -535,6 +628,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart5_default>;
> >                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_0
> > +                                               &qup_virt SLAVE_QUP_CORE_0>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_0>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >                 };
> > @@ -561,6 +659,14 @@
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -574,6 +680,11 @@
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -585,6 +696,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart6_default>;
> >                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -598,6 +714,14 @@
> >                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -609,6 +733,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart7_default>;
> >                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -622,6 +751,14 @@
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -635,6 +772,11 @@
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -646,6 +788,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart8_default>;
> >                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -659,6 +806,14 @@
> >                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -670,6 +825,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart9_default>;
> >                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -683,6 +843,14 @@
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -696,6 +864,11 @@
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -707,6 +880,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart10_default>;
> >                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -720,6 +898,14 @@
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>,
> > +                                               <&aggre2_noc MASTER_QUP_1
> > +                                               &mc_virt SLAVE_EBI1>;
> > +                               interconnect-names = "qup-core", "qup-config",
> > +                                                       "qup-memory";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -733,6 +919,11 @@
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> >                                 #address-cells = <1>;
> >                                 #size-cells = <0>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >
> > @@ -744,6 +935,11 @@
> >                                 pinctrl-names = "default";
> >                                 pinctrl-0 = <&qup_uart11_default>;
> >                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> > +                               interconnects = <&qup_virt MASTER_QUP_CORE_1
> > +                                               &qup_virt SLAVE_QUP_CORE_1>,
> > +                                               <&gem_noc MASTER_APPSS_PROC
> > +                                               &config_noc SLAVE_QUP_1>;
> > +                               interconnect-names = "qup-core", "qup-config";
> >                                 status = "disabled";
> >                         };
> >                 };
> > @@ -1051,6 +1247,9 @@
> >                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> >                                  <&gcc GCC_QSPI_CORE_CLK>;
> >                         clock-names = "iface", "core";
> > +                       interconnects = <&gem_noc MASTER_APPSS_PROC
> > +                                       &config_noc SLAVE_QSPI_0>;
> > +                       interconnect-names = "qspi-config";
> >                         status = "disabled";
> >                 };
> >
> > --
> > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
Matthias Kaehlcke March 9, 2020, 5:59 p.m. UTC | #9
Hi Akash,

do you plan to re-spin this series in the near future?

Thanks

Matthias

On Mon, Feb 17, 2020 at 06:59:59PM +0530, Akash Asthana wrote:
> dt-binding patch for UART, I2C and SPI.
>  - https://patchwork.kernel.org/patch/11385965/ [Convert QUP bindings
> 	to YAML and add ICC, pin swap doc]
> 
> dt-binding patch for QSPI.
>  - https://patchwork.kernel.org/cover/11386003/ [Convert QSPI binding
> 	to YAML and add interconnect doc]
> 
> Akash Asthana (6):
>   soc: qcom: geni: Support for ICC voting
>   tty: serial: qcom_geni_serial: Add interconnect support
>   i2c: i2c-qcom-geni: Add interconnect support
>   spi: spi-geni-qcom: Add interconnect support
>   spi: spi-qcom-qspi: Add interconnect support
>   arm64: dts: sc7180: Add interconnect for QUP and QSPI
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi  | 199 ++++++++++++++++++++++++++++++++++
>  drivers/i2c/busses/i2c-qcom-geni.c    |  84 +++++++++++++-
>  drivers/spi/spi-geni-qcom.c           |  65 ++++++++++-
>  drivers/spi/spi-qcom-qspi.c           |  38 ++++++-
>  drivers/tty/serial/qcom_geni_serial.c |  84 ++++++++++++--
>  include/linux/qcom-geni-se.h          |  31 ++++++
>  6 files changed, 481 insertions(+), 20 deletions(-)
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project