| Message ID | 20200508154359.7494-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: sve load/store improvements | expand |
Patchew URL: https://patchew.org/QEMU/20200508154359.7494-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200508154359.7494-1-richard.henderson@linaro.org
Subject: [PATCH v5 00/19] target/arm: sve load/store improvements
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
5531df6 target/arm: Remove sve_memopidx
32fcdbe target/arm: Reuse sve_probe_page for gather loads
18e6634 target/arm: Reuse sve_probe_page for scatter stores
1ed3f4e target/arm: Reuse sve_probe_page for gather first-fault loads
c8c5809 target/arm: Use SVEContLdSt for contiguous stores
ff13c74 target/arm: Update contiguous first-fault and no-fault loads
7a4fc9f target/arm: Use SVEContLdSt for multi-register contiguous loads
e162663 target/arm: Handle watchpoints in sve_ld1_r
0a4a70e target/arm: Use SVEContLdSt in sve_ld1_r
6bc90b5 target/arm: Adjust interface of sve_ld1_host_fn
17db59e target/arm: Add sve infrastructure for page lookup
b9da291 target/arm: Drop manual handling of set/clear_helper_retaddr
8fd1eb2 target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
474601a accel/tcg: Add endian-specific cpu_{ld, st}* operations
bdf03c8 accel/tcg: Add probe_access_flags
0c484ed accel/tcg: Adjust probe_access call to page_check_range
8a9847f accel/tcg: Add block comment for probe_access
7ae56c8 exec: Fix cpu_watchpoint_address_matches address length
3f79d9a exec: Add block comments for watchpoint routines
=== OUTPUT BEGIN ===
1/19 Checking commit 3f79d9ad401d (exec: Add block comments for watchpoint routines)
2/19 Checking commit 7ae56c835cf0 (exec: Fix cpu_watchpoint_address_matches address length)
3/19 Checking commit 8a9847f53fbc (accel/tcg: Add block comment for probe_access)
4/19 Checking commit 0c484ed7b14e (accel/tcg: Adjust probe_access call to page_check_range)
5/19 Checking commit bdf03c877b12 (accel/tcg: Add probe_access_flags)
6/19 Checking commit 474601a95614 (accel/tcg: Add endian-specific cpu_{ld, st}* operations)
7/19 Checking commit 8fd1eb2928fa (target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn)
ERROR: spaces required around that '*' (ctx:VxV)
#63: FILE: target/arm/sve_helper.c:4029:
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
^
ERROR: spaces required around that '*' (ctx:WxV)
#153: FILE: target/arm/sve_helper.c:4162:
+ sve_ldst1_tlb_fn *tlb_fn)
^
total: 2 errors, 0 warnings, 455 lines checked
Patch 7/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/19 Checking commit b9da291f2b6c (target/arm: Drop manual handling of set/clear_helper_retaddr)
9/19 Checking commit 17db59e78016 (target/arm: Add sve infrastructure for page lookup)
WARNING: Block comments use a leading /* on a separate line
#32: FILE: target/arm/sve_helper.c:1633:
+/* Big-endian hosts need to frob the byte indices. If the copy
total: 0 errors, 1 warnings, 281 lines checked
Patch 9/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/19 Checking commit 6bc90b548569 (target/arm: Adjust interface of sve_ld1_host_fn)
11/19 Checking commit 0a4a70e7e0ea (target/arm: Use SVEContLdSt in sve_ld1_r)
12/19 Checking commit e162663bddd0 (target/arm: Handle watchpoints in sve_ld1_r)
13/19 Checking commit 7a4fc9f72f73 (target/arm: Use SVEContLdSt for multi-register contiguous loads)
14/19 Checking commit ff13c741c638 (target/arm: Update contiguous first-fault and no-fault loads)
15/19 Checking commit c8c58097770c (target/arm: Use SVEContLdSt for contiguous stores)
16/19 Checking commit 1ed3f4ec9df2 (target/arm: Reuse sve_probe_page for gather first-fault loads)
17/19 Checking commit 18e66342e1c1 (target/arm: Reuse sve_probe_page for scatter stores)
18/19 Checking commit 32fcdbe6e7eb (target/arm: Reuse sve_probe_page for gather loads)
19/19 Checking commit 5531df6852bc (target/arm: Remove sve_memopidx)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20200508154359.7494-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
Patchew URL: https://patchew.org/QEMU/20200508154359.7494-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20200508154359.7494-1-richard.henderson@linaro.org
Subject: [PATCH v5 00/19] target/arm: sve load/store improvements
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
6459e7a target/arm: Remove sve_memopidx
7205242 target/arm: Reuse sve_probe_page for gather loads
edbaab9 target/arm: Reuse sve_probe_page for scatter stores
6fc3734 target/arm: Reuse sve_probe_page for gather first-fault loads
4a49d05 target/arm: Use SVEContLdSt for contiguous stores
c3adb6a target/arm: Update contiguous first-fault and no-fault loads
8a8b770 target/arm: Use SVEContLdSt for multi-register contiguous loads
389d29b target/arm: Handle watchpoints in sve_ld1_r
63d2628 target/arm: Use SVEContLdSt in sve_ld1_r
469f92b target/arm: Adjust interface of sve_ld1_host_fn
12bbd07 target/arm: Add sve infrastructure for page lookup
14e0e49 target/arm: Drop manual handling of set/clear_helper_retaddr
62e4351 target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
d904801 accel/tcg: Add endian-specific cpu_{ld, st}* operations
0551425 accel/tcg: Add probe_access_flags
64d0017 accel/tcg: Adjust probe_access call to page_check_range
35fd2ff accel/tcg: Add block comment for probe_access
7edaa91 exec: Fix cpu_watchpoint_address_matches address length
80f9aea exec: Add block comments for watchpoint routines
=== OUTPUT BEGIN ===
1/19 Checking commit 80f9aea15f56 (exec: Add block comments for watchpoint routines)
2/19 Checking commit 7edaa91b2b6b (exec: Fix cpu_watchpoint_address_matches address length)
3/19 Checking commit 35fd2ff72cf8 (accel/tcg: Add block comment for probe_access)
4/19 Checking commit 64d0017d5acf (accel/tcg: Adjust probe_access call to page_check_range)
5/19 Checking commit 055142569318 (accel/tcg: Add probe_access_flags)
6/19 Checking commit d90480155016 (accel/tcg: Add endian-specific cpu_{ld, st}* operations)
7/19 Checking commit 62e4351c804c (target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn)
ERROR: spaces required around that '*' (ctx:VxV)
#63: FILE: target/arm/sve_helper.c:4029:
+ TLB(env, addr, (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
^
ERROR: spaces required around that '*' (ctx:WxV)
#153: FILE: target/arm/sve_helper.c:4162:
+ sve_ldst1_tlb_fn *tlb_fn)
^
total: 2 errors, 0 warnings, 455 lines checked
Patch 7/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/19 Checking commit 14e0e496b39d (target/arm: Drop manual handling of set/clear_helper_retaddr)
9/19 Checking commit 12bbd07bd501 (target/arm: Add sve infrastructure for page lookup)
WARNING: Block comments use a leading /* on a separate line
#32: FILE: target/arm/sve_helper.c:1633:
+/* Big-endian hosts need to frob the byte indices. If the copy
total: 0 errors, 1 warnings, 281 lines checked
Patch 9/19 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/19 Checking commit 469f92b781ac (target/arm: Adjust interface of sve_ld1_host_fn)
11/19 Checking commit 63d26285f1a3 (target/arm: Use SVEContLdSt in sve_ld1_r)
12/19 Checking commit 389d29b65ff2 (target/arm: Handle watchpoints in sve_ld1_r)
13/19 Checking commit 8a8b7701adba (target/arm: Use SVEContLdSt for multi-register contiguous loads)
14/19 Checking commit c3adb6af934c (target/arm: Update contiguous first-fault and no-fault loads)
15/19 Checking commit 4a49d058ce11 (target/arm: Use SVEContLdSt for contiguous stores)
16/19 Checking commit 6fc3734e3350 (target/arm: Reuse sve_probe_page for gather first-fault loads)
17/19 Checking commit edbaab96ac2b (target/arm: Reuse sve_probe_page for scatter stores)
18/19 Checking commit 72052427669a (target/arm: Reuse sve_probe_page for gather loads)
19/19 Checking commit 6459e7a099d7 (target/arm: Remove sve_memopidx)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20200508154359.7494-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
On Fri, 8 May 2020 at 16:44, Richard Henderson <richard.henderson@linaro.org> wrote: > > Version 5 splits patch 4, as requested during review. > The patches remaining unreviewed are: > > 0004-accel-tcg-Adjust-probe_access-call-to-page_check_.patch > 0005-accel-tcg-Add-probe_access_flags.patch Applied to target-arm.next, thanks. Sorry it took me so long to figure out what was going on with patches 4/5. -- PMM
Version 5 splits patch 4, as requested during review. The patches remaining unreviewed are: 0004-accel-tcg-Adjust-probe_access-call-to-page_check_.patch 0005-accel-tcg-Add-probe_access_flags.patch r~ Original blurb: The goal here is to support MTE, but there's some cleanup to do. Technically, we have sufficient interfaces in cputlb.c now, but it requires multiple tlb lookups on different interfaces to do so. Adding probe_access_flags() allows probing the tlb and getting out some of the flags buried in the tlb comparator, such as TLB_MMIO and TLB_WATCHPOINT. In addition, we get no-fault semantics, which we don't have via probe_acccess(). Looking forward to MTE, we can examine the Tagged bit on a per-page basis and avoid dozens of mte_check calls that must be Unchecked. That comes later, in a new version of the MTE patch set, but I do add comments for where the checks should be added. Richard Henderson (19): exec: Add block comments for watchpoint routines exec: Fix cpu_watchpoint_address_matches address length accel/tcg: Add block comment for probe_access accel/tcg: Adjust probe_access call to page_check_range accel/tcg: Add probe_access_flags accel/tcg: Add endian-specific cpu_{ld,st}* operations target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn target/arm: Drop manual handling of set/clear_helper_retaddr target/arm: Add sve infrastructure for page lookup target/arm: Adjust interface of sve_ld1_host_fn target/arm: Use SVEContLdSt in sve_ld1_r target/arm: Handle watchpoints in sve_ld1_r target/arm: Use SVEContLdSt for multi-register contiguous loads target/arm: Update contiguous first-fault and no-fault loads target/arm: Use SVEContLdSt for contiguous stores target/arm: Reuse sve_probe_page for gather first-fault loads target/arm: Reuse sve_probe_page for scatter stores target/arm: Reuse sve_probe_page for gather loads target/arm: Remove sve_memopidx docs/devel/loads-stores.rst | 39 +- include/exec/cpu-all.h | 13 +- include/exec/cpu_ldst.h | 283 +++-- include/exec/exec-all.h | 39 + include/hw/core/cpu.h | 23 + target/arm/internals.h | 5 - accel/tcg/cputlb.c | 413 ++++--- accel/tcg/user-exec.c | 256 +++- exec.c | 2 +- target/arm/sve_helper.c | 2241 +++++++++++++++++++---------------- target/arm/translate-sve.c | 17 +- 11 files changed, 1999 insertions(+), 1332 deletions(-) -- 2.20.1