mbox series

[v2,0/9] target/arm: Misc cleanups surrounding TBI

Message ID 20200302175829.2183-1-richard.henderson@linaro.org
Headers show
Series target/arm: Misc cleanups surrounding TBI | expand

Message

Richard Henderson March 2, 2020, 5:58 p.m. UTC 
Changes for v2:
  * Improve commit message in "Optimize cpu_mmu_index".
  * Add "Introduce core_to_aa64_mmu_idx".
  * Use it in "Apply TBI to ESR_ELx in helper_exception_return".

Blurb for v1:

We have a bug at present wherein we do not supply the memory tag to
the memory system, so that on fault FAR_ELx does not contain the
correct value.

For system mode, we already handle ignoring TBI in get_phys_addr_lpae,
as long as we don't actually drop the tag during translation.
For user mode, we don't have that option, so for now we must simply
accept that we'll get the wrong value in the siginfo_t.

In the process of looking at all that I found:

  * Exception return was not applying TBI in copying ELR_ELx to PC,
    - Extracting the current mmu_idx can be improved,
    - Replicating the TBI bits can allow bit 55 to be used
      unconditionally, eliminating a test.

  * DC_ZVA was not handling TBI (now only for user-mode)
    - The helper need not have been in op_helper.c,
    - The helper could have better tcg markup.

  * TBI still applies when translation is disabled, and we weren't
    raising AddressSpace for bad physical addresses.

  * SVE hasn't been updated to handle TBI.  I have done nothing about
    this for now.  For the moment, system mode will work properly, while
    user-only will only work without tags.  I'll have to touch the same
    places to add MTE support, so it'll get done shortly.


r~


Richard Henderson (9):
  target/arm: Replicate TBI/TBID bits for single range regimes
  target/arm: Optimize cpu_mmu_index
  target/arm: Introduce core_to_aa64_mmu_idx
  target/arm: Apply TBI to ESR_ELx in helper_exception_return
  target/arm: Move helper_dc_zva to helper-a64.c
  target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
  target/arm: Clean address for DC ZVA
  target/arm: Check addresses for disabled regimes
  target/arm: Disable clean_data_tbi for system mode

 target/arm/cpu.h           |  23 ++++----
 target/arm/helper-a64.h    |   1 +
 target/arm/helper.h        |   1 -
 target/arm/internals.h     |   6 ++
 target/arm/helper-a64.c    | 114 ++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c        |  44 +++++++++++---
 target/arm/op_helper.c     |  93 ------------------------------
 target/arm/translate-a64.c |  15 ++++-
 8 files changed, 182 insertions(+), 115 deletions(-)

-- 
2.20.1

Comments

Peter Maydell March 5, 2020, 3:12 p.m. UTC | #1 
On Mon, 2 Mar 2020 at 17:58, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Changes for v2:

>   * Improve commit message in "Optimize cpu_mmu_index".

>   * Add "Introduce core_to_aa64_mmu_idx".

>   * Use it in "Apply TBI to ESR_ELx in helper_exception_return".


Applied 1-7 to target-arm.next, thanks.

-- PMM