| Message ID | 20200208125816.14954-4-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement PAN, ATS1E1, UAO | expand |
On Sat, 8 Feb 2020 at 12:58, Richard Henderson <richard.henderson@linaro.org> wrote: > > Include definitions for all of the bits in ID_MMFR3. > We already have a definition for ID_AA64MMFR1.PAN. > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) > return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; > } > > +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; > +} > + > +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) > +{ > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; > +} Didn't spot this before it hit master, but these feature test functions are looking at id->mvfr0, which is MVFR0, not MMFR3 ! Also they're using FIELD_EX64 on a 32-bit register: is there a reason for that? thanks -- PMM
On Fri, 14 Feb 2020 at 11:28, Peter Maydell <peter.maydell@linaro.org> wrote: > > On Sat, 8 Feb 2020 at 12:58, Richard Henderson > <richard.henderson@linaro.org> wrote: > > > > Include definitions for all of the bits in ID_MMFR3. > > We already have a definition for ID_AA64MMFR1.PAN. > > > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > > > @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) > > return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; > > } > > > > +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) > > +{ > > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; > > +} > > + > > +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) > > +{ > > + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; > > +} > > Didn't spot this before it hit master, but these feature > test functions are looking at id->mvfr0, which is MVFR0, not > MMFR3 ! > > Also they're using FIELD_EX64 on a 32-bit register: is there > a reason for that? I've been fiddling with the ID register stuff anyway, so I've written a patch that addresses these things. Due out in v2 of my PMU patchset. thanks -- PMM
On 2/14/20 3:28 AM, Peter Maydell wrote: >> +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) >> +{ >> + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; >> +} >> + >> +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) >> +{ >> + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; >> +} > > Didn't spot this before it hit master, but these feature > test functions are looking at id->mvfr0, which is MVFR0, not > MMFR3 ! > > Also they're using FIELD_EX64 on a 32-bit register: is there > a reason for that? Nope, both mistakes. Will fix, if you haven't done so already. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c63bceaaa5..08b2f5d73e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + FIELD(ID_MMFR4, SPECSEI, 0, 4) FIELD(ID_MMFR4, AC2, 4, 4) FIELD(ID_MMFR4, XNX, 8, 4) @@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; } +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; +} + /* * 64-bit feature tests via id registers. */ @@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;