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[v3,00/14] PHY: Add support for SERDES in TI's J721E SoC

Message ID 20191128104648.21894-1-kishon@ti.com
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Series PHY: Add support for SERDES in TI's J721E SoC | expand

Message

Kishon Vijay Abraham I Nov. 28, 2019, 10:46 a.m. UTC
TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII.
TI has a wrapper named WIZ to control input signals to Sierra and
Torrent SERDES.

This patch series:
 1) Add support to WIZ module present in TI's J721E SoC
 2) Adapt Cadence Sierra PHY driver to be used for J721E SoC

Changes from v2:
 *) Deprecate "phy_clk" binding
 *) Fix Rob's comment on dt bindings
        -> Include BSD-2-Clause license identifier
        -> drop "oneOf" and "items" for compatible
        -> Fixed "num-lanes" to include only scalar keywords
        -> Change to 32-bit address space for child nodes
*) Rename cmn_refclk/cmn_refclk1 to cmn_refclk_dig_div/
   cmn_refclk1_dig_div

Changes from v1:
 *) Change the dt binding Documentation of WIZ wrapper to YAML format
 *) Fix an issue in Sierra while doimg rmmod

Anil Varughese (1):
  phy: cadence: Sierra: Configure both lane cdb and common cdb registers
    for external SSC

Kishon Vijay Abraham I (13):
  dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
  phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional
    resources
  phy: cadence: Sierra: Use "regmap" for read and write to Sierra
    registers
  phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC
  phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops
  phy: cadence: Sierra: Modify register macro names to be in sync with
    Sierra user guide
  phy: cadence: Sierra: Get reset control "array" for each link
  phy: cadence: Sierra: Check for PLL lock during PHY power on
  phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
  phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div
    frequency to 25MHz
  phy: cadence: Sierra: Use correct dev pointer in
    cdns_sierra_phy_remove()
  dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
  phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

 .../bindings/phy/phy-cadence-sierra.txt       |  13 +-
 .../bindings/phy/ti,phy-j721e-wiz.yaml        | 158 +++
 drivers/phy/cadence/phy-cadence-sierra.c      | 699 +++++++++++---
 drivers/phy/ti/Kconfig                        |  15 +
 drivers/phy/ti/Makefile                       |   1 +
 drivers/phy/ti/phy-j721e-wiz.c                | 904 ++++++++++++++++++
 6 files changed, 1651 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
 create mode 100644 drivers/phy/ti/phy-j721e-wiz.c

-- 
2.17.1

Comments

Rob Herring (Arm) Dec. 13, 2019, 9:01 p.m. UTC | #1
On Thu, Nov 28, 2019 at 04:16:47PM +0530, Kishon Vijay Abraham I wrote:
> Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a

> PHY but a wrapper used to configure some of the input signals to the

> SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.

> 

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

> [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)

>  SERDES]

> Signed-off-by: Jyri Sarha <jsarha@ti.com>

> ---

>  .../bindings/phy/ti,phy-j721e-wiz.yaml        | 158 ++++++++++++++++++

>  1 file changed, 158 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

> 

> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

> new file mode 100644

> index 000000000000..5cd6f907f6af

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

> @@ -0,0 +1,158 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/

> +%YAML 1.2

> +---

> +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"

> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"

> +

> +title: TI J721E WIZ (SERDES Wrapper)

> +

> +maintainers:

> +  - Kishon Vijay Abraham I <kishon@ti.com>

> +

> +properties:

> +  compatible:

> +      enum:

> +          - ti,j721e-wiz-16g

> +          - ti,j721e-wiz-10g

> +

> +  power-domains:

> +    maxItems: 1

> +

> +  clocks:

> +    maxItems: 3

> +    description: clock-specifier to represent input to the WIZ

> +

> +  clock-names:

> +    items:

> +      - const: fck

> +      - const: core_ref_clk

> +      - const: ext_ref_clk

> +

> +  num-lanes:

> +    minimum: 1

> +    maximum: 4

> +

> +  "#address-cells":

> +    const: 1

> +

> +  "#size-cells":

> +    const: 1

> +

> +  "#reset-cells":

> +    const: 1

> +

> +  ranges: true

> +

> +  assigned-clocks:

> +    maxItems: 2

> +

> +  assigned-clock-parents:

> +    maxItems: 2

> +

> +patternProperties:

> +  "^pll[0|1]_refclk$":


Use '-' rather than '_' in node names.

> +    type: object

> +    description: |

> +      WIZ node should have subnodes for each of the PLLs present in

> +      the SERDES.


No properties in each of these nodes? They need to be defined.

> +

> +  "^cmn_refclk1?_dig_div$":

> +    type: object

> +    description: |

> +      WIZ node should have subnodes for each of the PMA common refclock

> +      provided by the SERDES.

> +

> +  "^refclk_dig$":

> +    type: object

> +    description: |

> +      WIZ node should have subnode for refclk_dig to select the reference

> +      clock source for the reference clock used in the PHY and PMA digital

> +      logic.

> +

> +  "^serdes@[0-9a-f]+$":

> +    type: object

> +    description: |

> +      WIZ node should have '1' subnode for the SERDES. It could be either

> +      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the

> +      bindings specified in

> +      Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

> +      Torrent SERDES should follow the bindings specified in

> +      Documentation/devicetree/bindings/phy/phy-cadence-dp.txt

> +

> +required:

> +  - compatible

> +  - power-domains

> +  - clocks

> +  - clock-names

> +  - num-lanes

> +  - "#address-cells"

> +  - "#size-cells"

> +  - "#reset-cells"

> +  - ranges

> +

> +examples:

> +  - |

> +    #include <dt-bindings/soc/ti,sci_pm_domain.h>

> +

> +    wiz@5000000 {

> +           compatible = "ti,j721e-wiz-16g";

> +           #address-cells = <1>;

> +           #size-cells = <1>;

> +           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;

> +           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;

> +           clock-names = "fck", "core_ref_clk", "ext_ref_clk";

> +           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;

> +           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;

> +           num-lanes = <2>;

> +           #reset-cells = <1>;

> +           ranges = <0x5000000 0x0 0x5000000 0x10000>;

> +

> +           pll0_refclk {

> +                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;

> +                  clock-output-names = "wiz1_pll0_refclk";


Kind of pointless with only 1 output.

> +                  #clock-cells = <0>;

> +                  assigned-clocks = <&wiz1_pll0_refclk>;

> +                  assigned-clock-parents = <&k3_clks 293 13>;

> +           };

> +

> +           pll1_refclk {

> +                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;

> +                  clock-output-names = "wiz1_pll1_refclk";

> +                  #clock-cells = <0>;

> +                  assigned-clocks = <&wiz1_pll1_refclk>;

> +                  assigned-clock-parents = <&k3_clks 293 0>;

> +           };

> +

> +           cmn_refclk_dig_div {

> +                  clocks = <&wiz1_refclk_dig>;

> +                  clock-output-names = "wiz1_cmn_refclk_dig_div";

> +                  #clock-cells = <0>;

> +           };

> +

> +           cmn_refclk1_dig_div {

> +                  clocks = <&wiz1_pll1_refclk>;

> +                  clock-output-names = "wiz1_cmn_refclk1_dig_div";

> +                  #clock-cells = <0>;

> +           };

> +

> +           refclk_dig {

> +                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;

> +                  clock-output-names = "wiz0_refclk_dig";

> +                  #clock-cells = <0>;

> +                  assigned-clocks = <&wiz0_refclk_dig>;

> +                  assigned-clock-parents = <&k3_clks 292 11>;

> +           };

> +

> +           serdes@5000000 {

> +                  compatible = "cdns,ti,sierra-phy-t0";

> +                  reg-names = "serdes";

> +                  reg = <0x5000000 0x10000>;

> +                  #address-cells = <1>;

> +                  #size-cells = <0>;

> +                  resets = <&serdes_wiz0 0>;

> +                  reset-names = "sierra_reset";

> +                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;

> +                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";

> +           };

> +    };

> -- 

> 2.17.1

>
Kishon Vijay Abraham I Dec. 16, 2019, 9:55 a.m. UTC | #2
Hi Rob,

On 14/12/19 2:31 am, Rob Herring wrote:
> On Thu, Nov 28, 2019 at 04:16:47PM +0530, Kishon Vijay Abraham I wrote:

>> Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a

>> PHY but a wrapper used to configure some of the input signals to the

>> SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes.

>>

>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

>> [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G)

>>   SERDES]

>> Signed-off-by: Jyri Sarha <jsarha@ti.com>

>> ---

>>   .../bindings/phy/ti,phy-j721e-wiz.yaml        | 158 ++++++++++++++++++

>>   1 file changed, 158 insertions(+)

>>   create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

>>

>> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

>> new file mode 100644

>> index 000000000000..5cd6f907f6af

>> --- /dev/null

>> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

>> @@ -0,0 +1,158 @@

>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

>> +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/

>> +%YAML 1.2

>> +---

>> +$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"

>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"

>> +

>> +title: TI J721E WIZ (SERDES Wrapper)

>> +

>> +maintainers:

>> +  - Kishon Vijay Abraham I <kishon@ti.com>

>> +

>> +properties:

>> +  compatible:

>> +      enum:

>> +          - ti,j721e-wiz-16g

>> +          - ti,j721e-wiz-10g

>> +

>> +  power-domains:

>> +    maxItems: 1

>> +

>> +  clocks:

>> +    maxItems: 3

>> +    description: clock-specifier to represent input to the WIZ

>> +

>> +  clock-names:

>> +    items:

>> +      - const: fck

>> +      - const: core_ref_clk

>> +      - const: ext_ref_clk

>> +

>> +  num-lanes:

>> +    minimum: 1

>> +    maximum: 4

>> +

>> +  "#address-cells":

>> +    const: 1

>> +

>> +  "#size-cells":

>> +    const: 1

>> +

>> +  "#reset-cells":

>> +    const: 1

>> +

>> +  ranges: true

>> +

>> +  assigned-clocks:

>> +    maxItems: 2

>> +

>> +  assigned-clock-parents:

>> +    maxItems: 2

>> +

>> +patternProperties:

>> +  "^pll[0|1]_refclk$":

> 

> Use '-' rather than '_' in node names.

> 

>> +    type: object

>> +    description: |

>> +      WIZ node should have subnodes for each of the PLLs present in

>> +      the SERDES.

> 

> No properties in each of these nodes? They need to be defined.

> 

>> +

>> +  "^cmn_refclk1?_dig_div$":

>> +    type: object

>> +    description: |

>> +      WIZ node should have subnodes for each of the PMA common refclock

>> +      provided by the SERDES.

>> +

>> +  "^refclk_dig$":

>> +    type: object

>> +    description: |

>> +      WIZ node should have subnode for refclk_dig to select the reference

>> +      clock source for the reference clock used in the PHY and PMA digital

>> +      logic.

>> +

>> +  "^serdes@[0-9a-f]+$":

>> +    type: object

>> +    description: |

>> +      WIZ node should have '1' subnode for the SERDES. It could be either

>> +      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the

>> +      bindings specified in

>> +      Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

>> +      Torrent SERDES should follow the bindings specified in

>> +      Documentation/devicetree/bindings/phy/phy-cadence-dp.txt

>> +

>> +required:

>> +  - compatible

>> +  - power-domains

>> +  - clocks

>> +  - clock-names

>> +  - num-lanes

>> +  - "#address-cells"

>> +  - "#size-cells"

>> +  - "#reset-cells"

>> +  - ranges

>> +

>> +examples:

>> +  - |

>> +    #include <dt-bindings/soc/ti,sci_pm_domain.h>

>> +

>> +    wiz@5000000 {

>> +           compatible = "ti,j721e-wiz-16g";

>> +           #address-cells = <1>;

>> +           #size-cells = <1>;

>> +           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;

>> +           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;

>> +           clock-names = "fck", "core_ref_clk", "ext_ref_clk";

>> +           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;

>> +           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;

>> +           num-lanes = <2>;

>> +           #reset-cells = <1>;

>> +           ranges = <0x5000000 0x0 0x5000000 0x10000>;

>> +

>> +           pll0_refclk {

>> +                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;

>> +                  clock-output-names = "wiz1_pll0_refclk";

> 

> Kind of pointless with only 1 output.


Okay. I'll fix all your comments in v4.

Thanks
Kishon