| Message ID | 20191211124608.887-1-kishon@ti.com |
|---|---|
| Headers | show |
| Series | Redesign MSI-X support in PCIe Endpoint Core | expand |
On Wed, Dec 11, 2019 at 06:16:04PM +0530, Kishon Vijay Abraham I wrote: > Existing MSI-X support in Endpoint core has limitations: > 1) MSIX table (which is mapped to a BAR) is not allocated by > anyone. Ideally this should be allocated by endpoint > function driver. > 2) Endpoint controller can choose any random BARs for MSIX > table (irrespective of whether the endpoint function driver > has allocated memory for it or not) > > In order to avoid these limitations, pci_epc_set_msix() is > modified to include BAR Indicator register (BIR) configuration > and MSIX table offset as arguments. This series also fixed MSIX > support in dwc driver and add MSI-X support in Cadence PCIe driver. > > The previous version of Cadence EP MSI-X support is @ [1]. > This series is created on top of [2] > > [1] -> https://patchwork.ozlabs.org/patch/971160/ > [2] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com > > Alan Douglas (1): > PCI: cadence: Add MSI-X support to Endpoint driver > > Kishon Vijay Abraham I (3): > PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments > PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table > address > PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt Trivial nits: - There's a mix of "MSI-X" and "MSIX" in the subjects, commit logs, and comments. I prefer "MSI-X" to match usage in the spec. - "Fixes:" tags need not include "commit". It doesn't *hurt* anything, but it takes up space that could be used for the subject. - Commit references typically use a 12-char SHA1. Again, doesn't hurt anything.
Existing MSI-X support in Endpoint core has limitations: 1) MSIX table (which is mapped to a BAR) is not allocated by anyone. Ideally this should be allocated by endpoint function driver. 2) Endpoint controller can choose any random BARs for MSIX table (irrespective of whether the endpoint function driver has allocated memory for it or not) In order to avoid these limitations, pci_epc_set_msix() is modified to include BAR Indicator register (BIR) configuration and MSIX table offset as arguments. This series also fixed MSIX support in dwc driver and add MSI-X support in Cadence PCIe driver. The previous version of Cadence EP MSI-X support is @ [1]. This series is created on top of [2] [1] -> https://patchwork.ozlabs.org/patch/971160/ [2] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com Alan Douglas (1): PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I (3): PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table address PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt .../pci/controller/cadence/pcie-cadence-ep.c | 112 +++++++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 10 ++ drivers/pci/controller/dwc/pci-keystone.c | 5 +- .../pci/controller/dwc/pcie-designware-ep.c | 61 +++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/endpoint/functions/pci-epf-test.c | 31 ++++- drivers/pci/endpoint/pci-epc-core.c | 7 +- drivers/pci/endpoint/pci-epf-core.c | 2 + include/linux/pci-epc.h | 6 +- include/linux/pci-epf.h | 15 +++ 10 files changed, 207 insertions(+), 43 deletions(-) -- 2.17.1