| Message ID | 20191203022937.1474-12-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > This is part of a reorganization to the set of mmu_idx. > The Secure regimes all have a single stage translation; > there is no point in pointing out that the idx is for stage1. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/cpu.h | 8 ++++---- > target/arm/internals.h | 4 ++-- > target/arm/translate.h | 2 +- > target/arm/helper.c | 26 +++++++++++++------------- > target/arm/translate-a64.c | 4 ++-- > target/arm/translate.c | 6 +++--- > 6 files changed, 25 insertions(+), 25 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 0714c52176..e8ee316e05 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2868,8 +2868,8 @@ typedef enum ARMMMUIdx { > ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A, > ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, > ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, > - ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, > - ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, > + ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A, > + ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A, > ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, > ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, > ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, > @@ -2894,8 +2894,8 @@ typedef enum ARMMMUIdxBit { > ARMMMUIdxBit_EL10_1 = 1 << 1, > ARMMMUIdxBit_S1E2 = 1 << 2, > ARMMMUIdxBit_S1E3 = 1 << 3, > - ARMMMUIdxBit_S1SE0 = 1 << 4, > - ARMMMUIdxBit_S1SE1 = 1 << 5, > + ARMMMUIdxBit_SE0 = 1 << 4, > + ARMMMUIdxBit_SE1 = 1 << 5, > ARMMMUIdxBit_Stage2 = 1 << 6, > ARMMMUIdxBit_MUser = 1 << 0, > ARMMMUIdxBit_MPriv = 1 << 1, > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 3fd1518f3b..3600bf9122 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) > case ARMMMUIdx_MUser: > return false; > case ARMMMUIdx_S1E3: > - case ARMMMUIdx_S1SE0: > - case ARMMMUIdx_S1SE1: > + case ARMMMUIdx_SE0: > + case ARMMMUIdx_SE1: > case ARMMMUIdx_MSPrivNegPri: > case ARMMMUIdx_MSUserNegPri: > case ARMMMUIdx_MSPriv: > diff --git a/target/arm/translate.h b/target/arm/translate.h > index dd24f91f26..3760159661 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -124,7 +124,7 @@ static inline int default_exception_el(DisasContext *s) > * exceptions can only be routed to ELs above 1, so we target the higher of > * 1 or the current EL. > */ > - return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) > + return (s->mmu_idx == ARMMMUIdx_SE0 && s->secure_routed_to_el3) > ? 3 : MAX(1, s->current_el); > } > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index a34accec20..377825431a 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3144,7 +3144,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > mmu_idx = ARMMMUIdx_Stage1_E1; > break; > case 1: > - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; > + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; > break; > default: > g_assert_not_reached(); > @@ -3154,13 +3154,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ > switch (el) { > case 3: > - mmu_idx = ARMMMUIdx_S1SE0; > + mmu_idx = ARMMMUIdx_SE0; > break; > case 2: > mmu_idx = ARMMMUIdx_Stage1_E0; > break; > case 1: > - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; > + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; > break; > default: > g_assert_not_reached(); > @@ -3214,7 +3214,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > case 0: > switch (ri->opc1) { > case 0: /* AT S1E1R, AT S1E1W */ > - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; > + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; > break; > case 4: /* AT S1E2R, AT S1E2W */ > mmu_idx = ARMMMUIdx_S1E2; > @@ -3227,13 +3227,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > } > break; > case 2: /* AT S1E0R, AT S1E0W */ > - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; > + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; > break; > case 4: /* AT S12E1R, AT S12E1W */ > - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; > + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; > break; > case 6: /* AT S12E0R, AT S12E0W */ > - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; > + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0; > break; > default: > g_assert_not_reached(); > @@ -3895,7 +3895,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, > static int vae1_tlbmask(CPUARMState *env) > { > if (arm_is_secure_below_el3(env)) { > - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; > + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; > } else { > return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; > } > @@ -3931,7 +3931,7 @@ static int vmalle1_tlbmask(CPUARMState *env) > * stage 1 translations. > */ > if (arm_is_secure_below_el3(env)) { > - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; > + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; > } else if (arm_feature(env, ARM_FEATURE_EL2)) { > return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2; > } else { > @@ -8569,9 +8569,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) > return 2; > case ARMMMUIdx_S1E3: > return 3; > - case ARMMMUIdx_S1SE0: > + case ARMMMUIdx_SE0: > return arm_el_is_aa64(env, 3) ? 1 : 3; > - case ARMMMUIdx_S1SE1: > + case ARMMMUIdx_SE1: > case ARMMMUIdx_Stage1_E0: > case ARMMMUIdx_Stage1_E1: > case ARMMMUIdx_MPrivNegPri: > @@ -8710,7 +8710,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) > static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) > { > switch (mmu_idx) { > - case ARMMMUIdx_S1SE0: > + case ARMMMUIdx_SE0: > case ARMMMUIdx_Stage1_E0: > case ARMMMUIdx_MUser: > case ARMMMUIdx_MSUser: > @@ -11150,7 +11150,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) > } > > if (el < 2 && arm_is_secure_below_el3(env)) { > - return ARMMMUIdx_S1SE0 + el; > + return ARMMMUIdx_SE0 + el; > } else { > return ARMMMUIdx_EL10_0 + el; > } > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 3a39315a6c..885c99f0c9 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *s) > case ARMMMUIdx_EL10_1: > useridx = ARMMMUIdx_EL10_0; > break; > - case ARMMMUIdx_S1SE1: > - useridx = ARMMMUIdx_S1SE0; > + case ARMMMUIdx_SE1: > + useridx = ARMMMUIdx_SE0; > break; > case ARMMMUIdx_Stage2: > g_assert_not_reached(); > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 1716bbb615..787e34f258 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *s) > case ARMMMUIdx_EL10_1: > return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); > case ARMMMUIdx_S1E3: > - case ARMMMUIdx_S1SE0: > - case ARMMMUIdx_S1SE1: > - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); > + case ARMMMUIdx_SE0: > + case ARMMMUIdx_SE1: > + return arm_to_core_mmu_idx(ARMMMUIdx_SE0); > case ARMMMUIdx_MUser: > case ARMMMUIdx_MPriv: > return arm_to_core_mmu_idx(ARMMMUIdx_MUser); -- Alex Bennée
On Tue, 3 Dec 2019 at 02:29, Richard Henderson <richard.henderson@linaro.org> wrote: > > This is part of a reorganization to the set of mmu_idx. > The Secure regimes all have a single stage translation; > there is no point in pointing out that the idx is for stage1. ...until we do support secure EL2, and then there might be a stage 2 again. -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0714c52176..e8ee316e05 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2868,8 +2868,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, @@ -2894,8 +2894,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_1 = 1 << 1, ARMMMUIdxBit_S1E2 = 1 << 2, ARMMMUIdxBit_S1E3 = 1 << 3, - ARMMMUIdxBit_S1SE0 = 1 << 4, - ARMMMUIdxBit_S1SE1 = 1 << 5, + ARMMMUIdxBit_SE0 = 1 << 4, + ARMMMUIdxBit_SE1 = 1 << 5, ARMMMUIdxBit_Stage2 = 1 << 6, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index 3fd1518f3b..3600bf9122 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f26..3760159661 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,7 +124,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the higher of * 1 or the current EL. */ - return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx == ARMMMUIdx_SE0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } diff --git a/target/arm/helper.c b/target/arm/helper.c index a34accec20..377825431a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3144,7 +3144,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3154,13 +3154,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx = ARMMMUIdx_S1SE0; + mmu_idx = ARMMMUIdx_SE0; break; case 2: mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3214,7 +3214,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_S1E2; @@ -3227,13 +3227,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3895,7 +3895,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -3931,7 +3931,7 @@ static int vmalle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2; } else { @@ -8569,9 +8569,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8710,7 +8710,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11150,7 +11150,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE0 + el; } else { return ARMMMUIdx_EL10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3a39315a6c..885c99f0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_EL10_1: useridx = ARMMMUIdx_EL10_0; break; - case ARMMMUIdx_S1SE1: - useridx = ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE1: + useridx = ARMMMUIdx_SE0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1716bbb615..787e34f258 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
This is part of a reorganization to the set of mmu_idx. The Secure regimes all have a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 26 +++++++++++++------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) -- 2.17.1