diff mbox series

[v4,38/40] target/arm: Pass more cpu state to arm_excp_unmasked

Message ID 20191203022937.1474-39-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Implement ARMv8.1-VHE | expand

Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m. UTC 
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

-- 
2.17.1

Comments

Philippe Mathieu-Daudé Dec. 3, 2019, 6:29 a.m. UTC | #1 
On 12/3/19 3:29 AM, Richard Henderson wrote:
> Avoid redundant computation of cpu state by passing it in

> from the caller, which has already computed it for itself.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> ---

>   target/arm/cpu.c | 22 ++++++++++++----------

>   1 file changed, 12 insertions(+), 10 deletions(-)

> 

> diff --git a/target/arm/cpu.c b/target/arm/cpu.c

> index a36344d4c7..7a1177b883 100644

> --- a/target/arm/cpu.c

> +++ b/target/arm/cpu.c

> @@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s)

>   }

>   

>   static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,

> -                                     unsigned int target_el)

> +                                     unsigned int target_el,

> +                                     unsigned int cur_el, bool secure,

> +                                     uint64_t hcr_el2)

>   {

>       CPUARMState *env = cs->env_ptr;

> -    unsigned int cur_el = arm_current_el(env);

> -    bool secure = arm_is_secure(env);

>       bool pstate_unmasked;

>       int8_t unmasked = 0;

> -    uint64_t hcr_el2;

>   

>       /*

>        * Don't take exceptions if they target a lower EL.

> @@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,

>           return false;

>       }

>   

> -    hcr_el2 = arm_hcr_el2_eff(env);

> -

>       switch (excp_idx) {

>       case EXCP_FIQ:

>           pstate_unmasked = !(env->daif & PSTATE_F);

> @@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

>       CPUARMState *env = cs->env_ptr;

>       uint32_t cur_el = arm_current_el(env);

>       bool secure = arm_is_secure(env);

> +    uint64_t hcr_el2 = arm_hcr_el2_eff(env);

>       uint32_t target_el;

>       uint32_t excp_idx;

>       bool ret = false;

> @@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

>       if (interrupt_request & CPU_INTERRUPT_FIQ) {

>           excp_idx = EXCP_FIQ;

>           target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);

> -        if (arm_excp_unmasked(cs, excp_idx, target_el)) {

> +        if (arm_excp_unmasked(cs, excp_idx, target_el,

> +                              cur_el, secure, hcr_el2)) {

>               cs->exception_index = excp_idx;

>               env->exception.target_el = target_el;

>               cc->do_interrupt(cs);

> @@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

>       if (interrupt_request & CPU_INTERRUPT_HARD) {

>           excp_idx = EXCP_IRQ;

>           target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);

> -        if (arm_excp_unmasked(cs, excp_idx, target_el)) {

> +        if (arm_excp_unmasked(cs, excp_idx, target_el,

> +                              cur_el, secure, hcr_el2)) {

>               cs->exception_index = excp_idx;

>               env->exception.target_el = target_el;

>               cc->do_interrupt(cs);

> @@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

>       if (interrupt_request & CPU_INTERRUPT_VIRQ) {

>           excp_idx = EXCP_VIRQ;

>           target_el = 1;

> -        if (arm_excp_unmasked(cs, excp_idx, target_el)) {

> +        if (arm_excp_unmasked(cs, excp_idx, target_el,

> +                              cur_el, secure, hcr_el2)) {

>               cs->exception_index = excp_idx;

>               env->exception.target_el = target_el;

>               cc->do_interrupt(cs);

> @@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

>       if (interrupt_request & CPU_INTERRUPT_VFIQ) {

>           excp_idx = EXCP_VFIQ;

>           target_el = 1;

> -        if (arm_excp_unmasked(cs, excp_idx, target_el)) {

> +        if (arm_excp_unmasked(cs, excp_idx, target_el,

> +                              cur_el, secure, hcr_el2)) {

>               cs->exception_index = excp_idx;

>               env->exception.target_el = target_el;

>               cc->do_interrupt(cs);

>
diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a36344d4c7..7a1177b883 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -411,14 +411,13 @@  static void arm_cpu_reset(CPUState *s)
 }
 
 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
-                                     unsigned int target_el)
+                                     unsigned int target_el,
+                                     unsigned int cur_el, bool secure,
+                                     uint64_t hcr_el2)
 {
     CPUARMState *env = cs->env_ptr;
-    unsigned int cur_el = arm_current_el(env);
-    bool secure = arm_is_secure(env);
     bool pstate_unmasked;
     int8_t unmasked = 0;
-    uint64_t hcr_el2;
 
     /*
      * Don't take exceptions if they target a lower EL.
@@ -429,8 +428,6 @@  static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
         return false;
     }
 
-    hcr_el2 = arm_hcr_el2_eff(env);
-
     switch (excp_idx) {
     case EXCP_FIQ:
         pstate_unmasked = !(env->daif & PSTATE_F);
@@ -535,6 +532,7 @@  bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     CPUARMState *env = cs->env_ptr;
     uint32_t cur_el = arm_current_el(env);
     bool secure = arm_is_secure(env);
+    uint64_t hcr_el2 = arm_hcr_el2_eff(env);
     uint32_t target_el;
     uint32_t excp_idx;
     bool ret = false;
@@ -542,7 +540,8 @@  bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     if (interrupt_request & CPU_INTERRUPT_FIQ) {
         excp_idx = EXCP_FIQ;
         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
-        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
             cs->exception_index = excp_idx;
             env->exception.target_el = target_el;
             cc->do_interrupt(cs);
@@ -552,7 +551,8 @@  bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     if (interrupt_request & CPU_INTERRUPT_HARD) {
         excp_idx = EXCP_IRQ;
         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
-        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
             cs->exception_index = excp_idx;
             env->exception.target_el = target_el;
             cc->do_interrupt(cs);
@@ -562,7 +562,8 @@  bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
         excp_idx = EXCP_VIRQ;
         target_el = 1;
-        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
             cs->exception_index = excp_idx;
             env->exception.target_el = target_el;
             cc->do_interrupt(cs);
@@ -572,7 +573,8 @@  bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
         excp_idx = EXCP_VFIQ;
         target_el = 1;
-        if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+        if (arm_excp_unmasked(cs, excp_idx, target_el,
+                              cur_el, secure, hcr_el2)) {
             cs->exception_index = excp_idx;
             env->exception.target_el = target_el;
             cc->do_interrupt(cs);