diff mbox series

[v6,03/20] target/arm: Split out rebuild_hflags_common_32

Message ID 20191011155546.14342-4-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Reduce overhead of cpu_get_tb_cpu_state | expand

Commit Message

Richard Henderson Oct. 11, 2019, 3:55 p.m. UTC 
Create a function to compute the values of the TBFLAG_A32 bits
that will be cached, and are used by all profiles.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Oct. 14, 2019, 3:53 p.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:

> Create a function to compute the values of the TBFLAG_A32 bits

> that will be cached, and are used by all profiles.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/helper.c | 16 +++++++++++-----

>  1 file changed, 11 insertions(+), 5 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 69da04786e..f05d042474 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,

>      return flags;

>  }

>

> +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,

> +                                         ARMMMUIdx mmu_idx, uint32_t flags)

> +{

> +    flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));

> +    flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));

> +

> +    return rebuild_hflags_common(env, fp_el, mmu_idx, flags);

> +}

> +

>  static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

>                                     ARMMMUIdx mmu_idx)

>  {

> @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>      ARMMMUIdx mmu_idx = arm_mmu_idx(env);

>      int current_el = arm_current_el(env);

>      int fp_el = fp_exception_el(env, current_el);

> -    uint32_t flags = 0;

> +    uint32_t flags;

>

>      if (is_a64(env)) {

>          *pc = env->pc;

> @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>          }

>      } else {

>          *pc = env->regs[15];

> +        flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);

>          flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);

>          flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);

>          flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);

>          flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);

> -        flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));

> -        flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));

>          if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)

>              || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {

>              flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);

> @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>              flags = FIELD_DP32(flags, TBFLAG_A32,

>                                 XSCALE_CPAR, env->cp15.c15_cpar);

>          }

> -

> -        flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);

>      }

>

>      /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine



--
Alex Bennée
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 69da04786e..f05d042474 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11070,6 +11070,15 @@  static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
     return flags;
 }
 
+static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
+                                         ARMMMUIdx mmu_idx, uint32_t flags)
+{
+    flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
+    flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
+
+    return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
+}
+
 static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
                                    ARMMMUIdx mmu_idx)
 {
@@ -11141,7 +11150,7 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     ARMMMUIdx mmu_idx = arm_mmu_idx(env);
     int current_el = arm_current_el(env);
     int fp_el = fp_exception_el(env, current_el);
-    uint32_t flags = 0;
+    uint32_t flags;
 
     if (is_a64(env)) {
         *pc = env->pc;
@@ -11151,12 +11160,11 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
         }
     } else {
         *pc = env->regs[15];
+        flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
         flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
         flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
         flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
         flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
-        flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
-        flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
             || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
             flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
@@ -11166,8 +11174,6 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
             flags = FIELD_DP32(flags, TBFLAG_A32,
                                XSCALE_CPAR, env->cp15.c15_cpar);
         }
-
-        flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags);
     }
 
     /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine