diff mbox series

[v2,32/68] target/arm: Convert SVC

Message ID 20190819213755.26175-33-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Convert aa32 base isa to decodetree | expand

Commit Message

Richard Henderson Aug. 19, 2019, 9:37 p.m. UTC
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 19 +++++++++++++------
 target/arm/a32.decode  |  4 ++++
 2 files changed, 17 insertions(+), 6 deletions(-)

-- 
2.17.1

Comments

Philippe Mathieu-Daudé Aug. 21, 2019, 1:21 p.m. UTC | #1
On 8/19/19 11:37 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


> ---

>  target/arm/translate.c | 19 +++++++++++++------

>  target/arm/a32.decode  |  4 ++++

>  2 files changed, 17 insertions(+), 6 deletions(-)

> 

> diff --git a/target/arm/translate.c b/target/arm/translate.c

> index 6b7b3df685..b6d8b7be8c 100644

> --- a/target/arm/translate.c

> +++ b/target/arm/translate.c

> @@ -9968,6 +9968,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)

>      return true;

>  }

>  

> +/*

> + * Supervisor call

> + */

> +

> +static bool trans_SVC(DisasContext *s, arg_SVC *a)

> +{

> +    gen_set_pc_im(s, s->base.pc_next);

> +    s->svc_imm = a->imm;

> +    s->base.is_jmp = DISAS_SWI;

> +    return true;

> +}

> +

>  /*

>   * Legacy decoder.

>   */

> @@ -10235,6 +10247,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

>          case 0x09:

>          case 0xa:

>          case 0xb:

> +        case 0xf:

>              /* All done in decodetree.  Reach here for illegal ops.  */

>              goto illegal_op;

>          case 0xc:

> @@ -10250,12 +10263,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

>                  goto illegal_op;

>              }

>              break;

> -        case 0xf:

> -            /* swi */

> -            gen_set_pc_im(s, s->base.pc_next);

> -            s->svc_imm = extract32(insn, 0, 24);

> -            s->base.is_jmp = DISAS_SWI;

> -            break;

>          default:

>          illegal_op:

>              unallocated_encoding(s);

> diff --git a/target/arm/a32.decode b/target/arm/a32.decode

> index 62c6f8562e..0bd952c069 100644

> --- a/target/arm/a32.decode

> +++ b/target/arm/a32.decode

> @@ -528,3 +528,7 @@ LDM_a32          ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16   &ldst_block

>  

>  B                .... 1010 ........................           @branch

>  BL               .... 1011 ........................           @branch

> +

> +# Supervisor call

> +

> +SVC              ---- 1111 imm:24                             &i

>
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6b7b3df685..b6d8b7be8c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9968,6 +9968,18 @@  static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
     return true;
 }
 
+/*
+ * Supervisor call
+ */
+
+static bool trans_SVC(DisasContext *s, arg_SVC *a)
+{
+    gen_set_pc_im(s, s->base.pc_next);
+    s->svc_imm = a->imm;
+    s->base.is_jmp = DISAS_SWI;
+    return true;
+}
+
 /*
  * Legacy decoder.
  */
@@ -10235,6 +10247,7 @@  static void disas_arm_insn(DisasContext *s, unsigned int insn)
         case 0x09:
         case 0xa:
         case 0xb:
+        case 0xf:
             /* All done in decodetree.  Reach here for illegal ops.  */
             goto illegal_op;
         case 0xc:
@@ -10250,12 +10263,6 @@  static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 goto illegal_op;
             }
             break;
-        case 0xf:
-            /* swi */
-            gen_set_pc_im(s, s->base.pc_next);
-            s->svc_imm = extract32(insn, 0, 24);
-            s->base.is_jmp = DISAS_SWI;
-            break;
         default:
         illegal_op:
             unallocated_encoding(s);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 62c6f8562e..0bd952c069 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -528,3 +528,7 @@  LDM_a32          ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16   &ldst_block
 
 B                .... 1010 ........................           @branch
 BL               .... 1011 ........................           @branch
+
+# Supervisor call
+
+SVC              ---- 1111 imm:24                             &i