| Message ID | 20190708135238.651483-1-arnd@arndb.de |
|---|---|
| State | Accepted |
| Commit | 5f65ae344f1493c9c6f0a1748da4ce3af71ab541 |
| Headers | show |
| Series | drm/amd/display: avoid 64-bit division | expand |
On 7/8/19 9:52 AM, Arnd Bergmann wrote: > On 32-bit architectures, dividing a 64-bit integer in the kernel > leads to a link error: > > ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! > ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! > > Change the two recently introduced instances to a multiply+shift > operation that is also much cheaper on 32-bit architectures. > We can do that here, since both of them are really 32-bit numbers > that change a few percent. > > Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") > Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > index c17db5c144aa..8dbf759eba45 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps( > * but the difference is minimal and is in a safe direction, > * which all works well around potential ambiguity of DP 1.4a spec. > */ > - long long fec_link_bw_kbps = link_bw_kbps * 970LL; > - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL); > + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, > + link_bw_kbps, 32); > } > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > index b35327bafbc5..70ac8a95d2db 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c > @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ > calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; > > // FCLK:UCLK ratio is 1.08 > - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; > + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); Even though the mul + shift will be faster here, I would prefer that this just be a div_u64 for clarity. Nicholas Kazlauskas > > calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? > min_dcfclk : min_fclk_required_by_uclk; >
Acked-by: Slava Abramov <slava.abramov@amd.com> Tested-by: Slava Abramov <slava.abramov@amd.com> ________________________________ From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de> Sent: Monday, July 8, 2019 9:52:08 AM To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter Cc: Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony Subject: [PATCH] drm/amd/display: avoid 64-bit division On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Signed-off-by: Arnd Bergmann <arnd@arndb.de> --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c17db5c144aa..8dbf759eba45 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps( * but the difference is minimal and is in a safe direction, * which all works well around potential ambiguity of DP 1.4a spec. */ - long long fec_link_bw_kbps = link_bw_kbps * 970LL; - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL); + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, + link_bw_kbps, 32); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index b35327bafbc5..70ac8a95d2db 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; -- 2.20.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"><!-- P {margin-top:0;margin-bottom:0;} --></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Acked-by: Slava Abramov <slava.abramov@amd.com></p> <p style="margin-top:0;margin-bottom:0">Tested-by: Slava Abramov <slava.abramov@amd.com></p> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de><br> <b>Sent:</b> Monday, July 8, 2019 9:52:08 AM<br> <b>To:</b> Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter<br> <b>Cc:</b> Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony<br> <b>Subject:</b> [PATCH] drm/amd/display: avoid 64-bit division</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">On 32-bit architectures, dividing a 64-bit integer in the kernel<br> leads to a link error:<br> <br> ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> <br> Change the two recently introduced instances to a multiply+shift<br> operation that is also much cheaper on 32-bit architectures.<br> We can do that here, since both of them are really 32-bit numbers<br> that change a few percent.<br> <br> Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")<br> Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV")<br> Signed-off-by: Arnd Bergmann <arnd@arndb.de><br> ---<br> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--<br> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-<br> 2 files changed, 3 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> index c17db5c144aa..8dbf759eba45 100644<br> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(<br> * but the difference is minimal and is in a safe direction,<br> * which all works well around potential ambiguity of DP 1.4a spec.<br> */<br> - long long fec_link_bw_kbps = link_bw_kbps * 970LL;<br> - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);<br> + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,<br> + link_bw_kbps, 32);<br> }<br> #endif<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> index b35327bafbc5..70ac8a95d2db 100644<br> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_<br> calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;<br> <br> // FCLK:UCLK ratio is 1.08<br> - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000;<br> + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);<br> <br> calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?<br> min_dcfclk : min_fclk_required_by_uclk;<br> -- <br> 2.20.0<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></div> </span></font></div> </body> </html>
Hi Arnd! Thanks for bisecting this issue. I wonder whether you are going to commit your patch or planning to update it and it's still in your work queue. We have one of our 32-bit builds failing because of this issue, so that I would like either to fix it or wait to your fix if it has chances to go upstream today. Sincerely, Slava Abramov ________________________________ From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de> Sent: Monday, July 8, 2019 9:52:08 AM To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter Cc: Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony Subject: [PATCH] drm/amd/display: avoid 64-bit division On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Signed-off-by: Arnd Bergmann <arnd@arndb.de> --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c17db5c144aa..8dbf759eba45 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps( * but the difference is minimal and is in a safe direction, * which all works well around potential ambiguity of DP 1.4a spec. */ - long long fec_link_bw_kbps = link_bw_kbps * 970LL; - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL); + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, + link_bw_kbps, 32); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index b35327bafbc5..70ac8a95d2db 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; -- 2.20.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"><!-- P {margin-top:0;margin-bottom:0;} --></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Hi Arnd!</p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0">Thanks for bisecting this issue.</p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0">I wonder whether you are going to commit your patch or planning to update it and it's still in your work queue. We have one of our 32-bit builds failing because of this issue, so that I would like either to fix it or wait to your fix if it has chances to go upstream today.</p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0">Sincerely,</p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0">Slava Abramov</p> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de><br> <b>Sent:</b> Monday, July 8, 2019 9:52:08 AM<br> <b>To:</b> Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter<br> <b>Cc:</b> Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony<br> <b>Subject:</b> [PATCH] drm/amd/display: avoid 64-bit division</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">On 32-bit architectures, dividing a 64-bit integer in the kernel<br> leads to a link error:<br> <br> ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> <br> Change the two recently introduced instances to a multiply+shift<br> operation that is also much cheaper on 32-bit architectures.<br> We can do that here, since both of them are really 32-bit numbers<br> that change a few percent.<br> <br> Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")<br> Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV")<br> Signed-off-by: Arnd Bergmann <arnd@arndb.de><br> ---<br> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--<br> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-<br> 2 files changed, 3 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> index c17db5c144aa..8dbf759eba45 100644<br> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(<br> * but the difference is minimal and is in a safe direction,<br> * which all works well around potential ambiguity of DP 1.4a spec.<br> */<br> - long long fec_link_bw_kbps = link_bw_kbps * 970LL;<br> - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);<br> + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,<br> + link_bw_kbps, 32);<br> }<br> #endif<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> index b35327bafbc5..70ac8a95d2db 100644<br> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_<br> calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;<br> <br> // FCLK:UCLK ratio is 1.08<br> - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000;<br> + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);<br> <br> calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?<br> min_dcfclk : min_fclk_required_by_uclk;<br> -- <br> 2.20.0<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></div> </span></font></div> </body> </html>
I'll just apply Arnd's patch. If the display team wants to adjust it later to clarify the operation, they should go ahead as a follow up patch. Thanks, Alex ________________________________ From: Abramov, Slava Sent: Tuesday, July 9, 2019 12:31 PM To: Arnd Bergmann; Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter Cc: Liu, Charlene; Park, Chris; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony Subject: Re: [PATCH] drm/amd/display: avoid 64-bit division Hi Arnd! Thanks for bisecting this issue. I wonder whether you are going to commit your patch or planning to update it and it's still in your work queue. We have one of our 32-bit builds failing because of this issue, so that I would like either to fix it or wait to your fix if it has chances to go upstream today. Sincerely, Slava Abramov ________________________________ From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de> Sent: Monday, July 8, 2019 9:52:08 AM To: Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter Cc: Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony Subject: [PATCH] drm/amd/display: avoid 64-bit division On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Signed-off-by: Arnd Bergmann <arnd@arndb.de> --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c17db5c144aa..8dbf759eba45 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps( * but the difference is minimal and is in a safe direction, * which all works well around potential ambiguity of DP 1.4a spec. */ - long long fec_link_bw_kbps = link_bw_kbps * 970LL; - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL); + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, + link_bw_kbps, 32); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index b35327bafbc5..70ac8a95d2db 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; -- 2.20.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> I'll just apply Arnd's patch. If the display team wants to adjust it later to clarify the operation, they should go ahead as a follow up patch.</div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Thanks,<br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Alex<br> </div> <div id="appendonsend"></div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Abramov, Slava<br> <b>Sent:</b> Tuesday, July 9, 2019 12:31 PM<br> <b>To:</b> Arnd Bergmann; Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter<br> <b>Cc:</b> Liu, Charlene; Park, Chris; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony<br> <b>Subject:</b> Re: [PATCH] drm/amd/display: avoid 64-bit division</font> <div> </div> </div> <style type="text/css" style="display:none"> <!-- p {margin-top:0; margin-bottom:0} --> </style> <div dir="ltr"> <div id="x_divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Helvetica,sans-serif"> <p style="margin-top:0; margin-bottom:0">Hi Arnd!</p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0">Thanks for bisecting this issue.</p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0">I wonder whether you are going to commit your patch or planning to update it and it's still in your work queue. We have one of our 32-bit builds failing because of this issue, so that I would like either to fix it or wait to your fix if it has chances to go upstream today.</p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0">Sincerely,</p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0">Slava Abramov</p> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Arnd Bergmann <arnd@arndb.de><br> <b>Sent:</b> Monday, July 8, 2019 9:52:08 AM<br> <b>To:</b> Wentland, Harry; Li, Sun peng (Leo); Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter<br> <b>Cc:</b> Liu, Charlene; Park, Chris; Arnd Bergmann; Cheng, Tony; Francis, David; linux-kernel@vger.kernel.org; amd-gfx@lists.freedesktop.org; Cornij, Nikola; Laktyushkin, Dmytro; dri-devel@lists.freedesktop.org; Lei, Jun; Lakha, Bhawanpreet; Koo, Anthony<br> <b>Subject:</b> [PATCH] drm/amd/display: avoid 64-bit division</font> <div> </div> </div> <div class="x_BodyFragment"><font size="2"><span style="font-size:11pt"> <div class="x_PlainText">On 32-bit architectures, dividing a 64-bit integer in the kernel<br> leads to a link error:<br> <br> ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!<br> <br> Change the two recently introduced instances to a multiply+shift<br> operation that is also much cheaper on 32-bit architectures.<br> We can do that here, since both of them are really 32-bit numbers<br> that change a few percent.<br> <br> Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")<br> Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV")<br> Signed-off-by: Arnd Bergmann <arnd@arndb.de><br> ---<br> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--<br> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-<br> 2 files changed, 3 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> index c17db5c144aa..8dbf759eba45 100644<br> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c<br> @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(<br> * but the difference is minimal and is in a safe direction,<br> * which all works well around potential ambiguity of DP 1.4a spec.<br> */<br> - long long fec_link_bw_kbps = link_bw_kbps * 970LL;<br> - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);<br> + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,<br> + link_bw_kbps, 32);<br> }<br> #endif<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> index b35327bafbc5..70ac8a95d2db 100644<br> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c<br> @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_<br> calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;<br> <br> // FCLK:UCLK ratio is 1.08<br> - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000;<br> + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);<br> <br> calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?<br> min_dcfclk : min_fclk_required_by_uclk;<br> -- <br> 2.20.0<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></div> </span></font></div> </div> </body> </html>
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index c17db5c144aa..8dbf759eba45 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps( * but the difference is minimal and is in a safe direction, * which all works well around potential ambiguity of DP 1.4a spec. */ - long long fec_link_bw_kbps = link_bw_kbps * 970LL; - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL); + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, + link_bw_kbps, 32); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index b35327bafbc5..70ac8a95d2db 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; // FCLK:UCLK ratio is 1.08 - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk;
On 32-bit architectures, dividing a 64-bit integer in the kernel leads to a link error: ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Change the two recently introduced instances to a multiply+shift operation that is also much cheaper on 32-bit architectures. We can do that here, since both of them are really 32-bit numbers that change a few percent. Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link") Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV") Signed-off-by: Arnd Bergmann <arnd@arndb.de> --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)