| Message ID | 20190506120458.25842-2-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 | expand |
Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam: > Enable SPI1 exposed on both Low and High speed expansion connectors > of Ficus. SPI1 has 3 different chip selects wired as below: > > CS0 - Serial Flash (unpopulated) > CS1 - Low Speed expansion > CS2 - High Speed expansion > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > index 027d428917b8..9baa378fc770 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > @@ -146,6 +146,12 @@ > }; > }; > > +&spi1 { > + /* On both Low speed and High speed expansion */ > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>; cs0 should still be part of the cs-gpios though (gpio1 RK_PB2). The flash is part of the schematics, so there might be board with it pre-populated or people might put a flash chip on it. Also please use the constants for pin specification (RK_PA6, RK_PA7 above) Heiko > + status = "okay"; > +}; > + > &usbdrd_dwc3_0 { > dr_mode = "host"; > }; >
On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote: > Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam: > > Enable SPI1 exposed on both Low and High speed expansion connectors > > of Ficus. SPI1 has 3 different chip selects wired as below: > > > > CS0 - Serial Flash (unpopulated) > > CS1 - Low Speed expansion > > CS2 - High Speed expansion > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > index 027d428917b8..9baa378fc770 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > @@ -146,6 +146,12 @@ > > }; > > }; > > > > +&spi1 { > > + /* On both Low speed and High speed expansion */ > > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>; > > cs0 should still be part of the cs-gpios though (gpio1 RK_PB2). > The flash is part of the schematics, so there might be board with > it pre-populated or people might put a flash chip on it. > Why? CS0 is owned by the SPI controller itself, so we can't use it as a GPIO. Otherwise, we need to change the pinctrl definition of it, which doesn't look good to me. > Also please use the constants for pin specification (RK_PA6, RK_PA7 above) > Sure. Thanks, Mani > > Heiko > > > + status = "okay"; > > +}; > > + > > &usbdrd_dwc3_0 { > > dr_mode = "host"; > > }; > > > > > >
Am Dienstag, 7. Mai 2019, 13:36:35 CEST schrieb Manivannan Sadhasivam: > On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote: > > Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam: > > > Enable SPI1 exposed on both Low and High speed expansion connectors > > > of Ficus. SPI1 has 3 different chip selects wired as below: > > > > > > CS0 - Serial Flash (unpopulated) > > > CS1 - Low Speed expansion > > > CS2 - High Speed expansion > > > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > --- > > > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++ > > > 1 file changed, 6 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > > index 027d428917b8..9baa378fc770 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts > > > @@ -146,6 +146,12 @@ > > > }; > > > }; > > > > > > +&spi1 { > > > + /* On both Low speed and High speed expansion */ > > > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>; > > > > cs0 should still be part of the cs-gpios though (gpio1 RK_PB2). > > The flash is part of the schematics, so there might be board with > > it pre-populated or people might put a flash chip on it. > > > > Why? CS0 is owned by the SPI controller itself, so we can't use it as > a GPIO. Otherwise, we need to change the pinctrl definition of it, which > doesn't look good to me. Ok, but are you sure mixing both pinctrl-based chip-select with gpio-based chip-select will actually work when the spi-flash is populated? But it looks like you're right in that spi_set_cs() checks for a gpio-cs first and falls back to the controller-based chip-select. So I guess this can stay as it is. > > > Also please use the constants for pin specification (RK_PA6, RK_PA7 above) > > > > Sure. Thanks Heiko > > Thanks, > Mani > > > > > Heiko > > > > > + status = "okay"; > > > +}; > > > + > > > &usbdrd_dwc3_0 { > > > dr_mode = "host"; > > > }; > > > > > > > > > > > >
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts index 027d428917b8..9baa378fc770 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -146,6 +146,12 @@ }; }; +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>; + status = "okay"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; };
Enable SPI1 exposed on both Low and High speed expansion connectors of Ficus. SPI1 has 3 different chip selects wired as below: CS0 - Serial Flash (unpopulated) CS1 - Low Speed expansion CS2 - High Speed expansion Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1