mbox series

[for-4.1,v2,00/36] tcg: Move the softmmu tlb to CPUNegativeOffsetState

Message ID 20190328230404.12909-1-richard.henderson@linaro.org
Headers show
Series tcg: Move the softmmu tlb to CPUNegativeOffsetState | expand

Message

Richard Henderson March 28, 2019, 11:03 p.m. UTC
Changes from v1->v2:
  * Add cpu_set_cpustate_pointers.
  * Add icount_decr_ptr to CPUState.

Blurb from v1:

This started merely as an attempt to reduce the size of each
softmmu lookup by using smaller offsets from env.  But in the
end it also represents a significant cleanup in the boilerplate
that each target must define.

With respect to the initial goal, here are the relevant code
snips generated for loading the mask & table fields for a
qemu_ld from an aarch64 guest on the indicated host.

BEFORE:

x86_64:
0x7f9698c5f73b:  48 23 bd 98 32 00 00     andq     0x3298(%rbp), %rdi
0x7f9698c5f742:  48 03 bd d8 32 00 00     addq     0x32d8(%rbp), %rdi

aarch64:
0xffff9e001e28:  91400e61  add      x1, x19, #3, lsl #12
0xffff9e001e2c:  f9414c20  ldr      x0, [x1, #0x298]
0xffff9e001e30:  f9416c21  ldr      x1, [x1, #0x2d8]

aarch32:
0xa2b7f0d4:  e2862a03  add      r2, r6, #0x3000
0xa2b7f0d8:  e592c20c  ldr      ip, [r2, #0x20c]
0xa2b7f0dc:  e592222c  ldr      r2, [r2, #0x22c]

AFTER:

x86_64:
0x7fa40a000154:  48 23 7d e0              andq     -0x20(%rbp), %rdi
0x7fa40a000158:  48 03 7d e8              addq     -0x18(%rbp), %rdi

aarch64:
0xffffa20001b4:  a97e0660  ldp      x0, x1, [x19, #-0x20]

aarch32:
0xa2c7f0d4:  e14604d8  ldrd     r0, r1, [r6, #-0x48]

The other tcg hosts do not see as significant difference.  PPC and
mips have 16-bit signed offsets, and have no load-pair/multiple.
S390x has 20-bit signed offsets and, like x86, uses a read-operate
instruction form.  Sparc and RISC-V have 13 and 12-bit signed offsets
respectively, and so do avoid an extra add insn in this case, but
do not have load-pair/multiple.

All that said, in the end I'm most happy with the diffstat result.


r~



Richard Henderson (36):
  tcg: Fold CPUTLBWindow into CPUTLBDesc
  tcg: Split out target/arch/cpu-param.h
  tcg: Create struct CPUTLB
  cpu: Define CPUArchState with typedef
  cpu: Define ArchCPU
  cpu: Replace ENV_GET_CPU with env_cpu
  cpu: Introduce env_archcpu
  target/alpha: Use env_cpu, env_archcpu
  target/arm: Use env_cpu, env_archcpu
  target/cris: Use env_cpu, env_archcpu
  target/hppa: Use env_cpu, env_archcpu
  target/i386: Use env_cpu, env_archcpu
  target/lm32: Use env_cpu, env_archcpu
  target/m68k: Use env_cpu, env_archcpu
  target/microblaze: Use env_cpu, env_archcpu
  target/mips: Use env_cpu, env_archcpu
  target/moxie: Use env_cpu, env_archcpu
  target/nios2: Use env_cpu, env_archcpu
  target/openrisc: Use env_cpu, env_archcpu
  target/ppc: Use env_cpu, env_archcpu
  target/riscv: Use env_cpu, env_archcpu
  target/s390x: Use env_cpu, env_archcpu
  target/sh4: Use env_cpu, env_archcpu
  target/sparc: Use env_cpu, env_archcpu
  target/tilegx: Use env_cpu
  target/tricore: Use env_cpu
  target/unicore32: Use env_cpu, env_archcpu
  target/xtensa: Use env_cpu, env_archcpu
  cpu: Move ENV_OFFSET to exec/gen-icount.h
  cpu: Introduce cpu_set_cpustate_pointers
  cpu: Introduce CPUNegativeOffsetState
  cpu: Move icount_decr to CPUNegativeOffsetState
  cpu: Move the softmmu tlb to CPUNegativeOffsetState
  cpu: Remove CPU_COMMON
  tcg/aarch64: Use LDP to load tlb mask+table
  tcg/arm: Use LDRD to load tlb mask+table

 accel/tcg/atomic_template.h               |   8 +-
 accel/tcg/softmmu_template.h              |  24 +--
 include/exec/cpu-all.h                    |  58 +++++++
 include/exec/cpu-defs.h                   | 113 ++++++++-----
 include/exec/cpu_ldst.h                   |   6 +-
 include/exec/cpu_ldst_template.h          |   6 +-
 include/exec/cpu_ldst_useronly_template.h |   6 +-
 include/exec/gen-icount.h                 |  14 +-
 include/exec/softmmu-semi.h               |  16 +-
 include/qom/cpu.h                         |  40 ++---
 linux-user/cpu_loop-common.h              |   2 +-
 linux-user/m68k/target_cpu.h              |   2 +-
 target/alpha/cpu-param.h                  |  19 +++
 target/alpha/cpu.h                        |  40 +----
 target/arm/cpu-param.h                    |  22 +++
 target/arm/cpu.h                          |  52 +-----
 target/cris/cpu-param.h                   |   5 +
 target/cris/cpu.h                         |  25 +--
 target/hppa/cpu-param.h                   |  22 +++
 target/hppa/cpu.h                         |  38 +----
 target/i386/cpu-param.h                   |  14 ++
 target/i386/cpu.h                         |  40 +----
 target/lm32/cpu-param.h                   |   5 +
 target/lm32/cpu.h                         |  25 +--
 target/m68k/cpu-param.h                   |   9 +
 target/m68k/cpu.h                         |  28 +---
 target/microblaze/cpu-param.h             |   6 +
 target/microblaze/cpu.h                   |  63 +++----
 target/mips/cpu-param.h                   |  18 ++
 target/mips/cpu.h                         |  21 +--
 target/mips/mips-defs.h                   |  15 --
 target/moxie/cpu-param.h                  |   5 +
 target/moxie/cpu.h                        |  29 +---
 target/nios2/cpu-param.h                  |   9 +
 target/nios2/cpu.h                        |  33 +---
 target/openrisc/cpu-param.h               |   5 +
 target/openrisc/cpu.h                     |  31 +---
 target/ppc/cpu-param.h                    |  25 +++
 target/ppc/cpu.h                          |  54 +-----
 target/ppc/helper_regs.h                  |   4 +-
 target/riscv/cpu-param.h                  |  11 ++
 target/riscv/cpu.h                        |  35 +---
 target/s390x/cpu-param.h                  |   5 +
 target/s390x/cpu.h                        |  31 +---
 target/sh4/cpu-param.h                    |   9 +
 target/sh4/cpu.h                          |  30 +---
 target/sparc/cpu-param.h                  |  17 ++
 target/sparc/cpu.h                        |  36 +---
 target/tilegx/cpu-param.h                 |   5 +
 target/tilegx/cpu.h                       |  23 +--
 target/tricore/cpu-param.h                |   5 +
 target/tricore/cpu.h                      |  22 +--
 target/tricore/tricore-defs.h             |   5 -
 target/unicore32/cpu-param.h              |   5 +
 target/unicore32/cpu.h                    |  24 +--
 target/xtensa/cpu-param.h                 |   9 +
 target/xtensa/cpu.h                       |  40 ++---
 accel/tcg/cpu-exec.c                      |  23 +--
 accel/tcg/cputlb.c                        | 193 +++++++++++-----------
 accel/tcg/tcg-all.c                       |   6 +-
 accel/tcg/tcg-runtime.c                   |   4 +-
 accel/tcg/translate-all.c                 |  10 +-
 accel/tcg/user-exec.c                     |   2 +-
 bsd-user/main.c                           |   5 +-
 bsd-user/syscall.c                        |   6 +-
 cpus.c                                    |   9 +-
 hw/i386/kvmvapic.c                        |   4 +-
 hw/i386/pc.c                              |   2 +-
 hw/intc/mips_gic.c                        |   2 +-
 hw/mips/mips_int.c                        |   2 +-
 hw/nios2/cpu_pic.c                        |   5 +-
 hw/ppc/ppc.c                              |  18 +-
 hw/ppc/ppc405_uc.c                        |   2 +-
 hw/ppc/ppc_booke.c                        |   4 +-
 hw/sparc/leon3.c                          |   4 +-
 hw/sparc/sun4m.c                          |   4 +-
 hw/sparc64/sparc64.c                      |   2 +-
 hw/unicore32/puv3.c                       |   2 +-
 hw/xtensa/pic_cpu.c                       |   2 +-
 linux-user/aarch64/cpu_loop.c             |   6 +-
 linux-user/aarch64/signal.c               |   4 +-
 linux-user/alpha/cpu_loop.c               |   2 +-
 linux-user/arm/cpu_loop.c                 |   4 +-
 linux-user/cris/cpu_loop.c                |   4 +-
 linux-user/elfload.c                      |   6 +-
 linux-user/hppa/cpu_loop.c                |   2 +-
 linux-user/i386/cpu_loop.c                |   2 +-
 linux-user/i386/signal.c                  |   2 +-
 linux-user/m68k-sim.c                     |   3 +-
 linux-user/m68k/cpu_loop.c                |   4 +-
 linux-user/main.c                         |   2 +-
 linux-user/microblaze/cpu_loop.c          |   2 +-
 linux-user/mips/cpu_loop.c                |   4 +-
 linux-user/nios2/cpu_loop.c               |   2 +-
 linux-user/openrisc/cpu_loop.c            |   2 +-
 linux-user/ppc/cpu_loop.c                 |   2 +-
 linux-user/riscv/cpu_loop.c               |   4 +-
 linux-user/s390x/cpu_loop.c               |   2 +-
 linux-user/sh4/cpu_loop.c                 |   2 +-
 linux-user/signal.c                       |   8 +-
 linux-user/sparc/cpu_loop.c               |   2 +-
 linux-user/syscall.c                      |  26 +--
 linux-user/tilegx/cpu_loop.c              |   2 +-
 linux-user/uname.c                        |   2 +-
 linux-user/vm86.c                         |  18 +-
 linux-user/xtensa/cpu_loop.c              |   2 +-
 qom/cpu.c                                 |   4 +-
 target/alpha/cpu.c                        |   3 +-
 target/alpha/helper.c                     |   8 +-
 target/alpha/sys_helper.c                 |   8 +-
 target/arm/arm-semi.c                     |   4 +-
 target/arm/cpu.c                          |   3 +-
 target/arm/cpu64.c                        |   2 +-
 target/arm/helper-a64.c                   |   4 +-
 target/arm/helper.c                       | 160 +++++++++---------
 target/arm/op_helper.c                    |  21 ++-
 target/arm/translate-a64.c                |   4 +-
 target/arm/translate.c                    |   2 +-
 target/arm/vfp_helper.c                   |   2 +-
 target/cris/cpu.c                         |   3 +-
 target/cris/mmu.c                         |   3 +-
 target/cris/op_helper.c                   |  10 +-
 target/cris/translate.c                   |   2 +-
 target/hppa/cpu.c                         |   2 +-
 target/hppa/helper.c                      |   3 +-
 target/hppa/int_helper.c                  |   4 +-
 target/hppa/mem_helper.c                  |  10 +-
 target/hppa/op_helper.c                   |  10 +-
 target/i386/bpt_helper.c                  |   4 +-
 target/i386/cpu.c                         |   7 +-
 target/i386/excp_helper.c                 |   2 +-
 target/i386/fpu_helper.c                  |   2 +-
 target/i386/hax-all.c                     |   6 +-
 target/i386/helper.c                      |  16 +-
 target/i386/hvf/x86_decode.c              |  22 +--
 target/i386/hvf/x86_emu.c                 |  60 ++++---
 target/i386/mem_helper.c                  |   4 +-
 target/i386/misc_helper.c                 |  24 ++-
 target/i386/seg_helper.c                  |  14 +-
 target/i386/smm_helper.c                  |   4 +-
 target/i386/svm_helper.c                  |  22 +--
 target/lm32/cpu.c                         |   3 +-
 target/lm32/helper.c                      |  19 +--
 target/lm32/op_helper.c                   |   6 +-
 target/lm32/translate.c                   |   2 +-
 target/m68k/cpu.c                         |   4 +-
 target/m68k/helper.c                      |  33 ++--
 target/m68k/m68k-semi.c                   |   4 +-
 target/m68k/op_helper.c                   |  14 +-
 target/m68k/translate.c                   |   4 +-
 target/microblaze/cpu.c                   |   3 +-
 target/microblaze/mmu.c                   |   5 +-
 target/microblaze/op_helper.c             |   2 +-
 target/microblaze/translate.c             |   2 +-
 target/mips/cpu.c                         |   3 +-
 target/mips/helper.c                      |  15 +-
 target/mips/op_helper.c                   |  25 ++-
 target/mips/translate.c                   |   3 +-
 target/mips/translate_init.inc.c          |   4 +-
 target/moxie/cpu.c                        |   3 +-
 target/moxie/helper.c                     |   6 +-
 target/moxie/translate.c                  |   2 +-
 target/nios2/cpu.c                        |   6 +-
 target/nios2/mmu.c                        |  14 +-
 target/nios2/op_helper.c                  |   2 +-
 target/openrisc/cpu.c                     |   3 +-
 target/openrisc/exception_helper.c        |   5 +-
 target/openrisc/sys_helper.c              |   8 +-
 target/ppc/excp_helper.c                  |  14 +-
 target/ppc/fpu_helper.c                   |  14 +-
 target/ppc/kvm.c                          |   5 +-
 target/ppc/misc_helper.c                  |  22 +--
 target/ppc/mmu-hash64.c                   |  14 +-
 target/ppc/mmu_helper.c                   | 118 ++++++-------
 target/ppc/translate_init.inc.c           |  90 +++++-----
 target/riscv/cpu.c                        |   3 +-
 target/riscv/cpu_helper.c                 |   4 +-
 target/riscv/csr.c                        |  12 +-
 target/riscv/op_helper.c                  |   8 +-
 target/s390x/cc_helper.c                  |   5 +-
 target/s390x/cpu.c                        |   9 +-
 target/s390x/diag.c                       |   2 +-
 target/s390x/excp_helper.c                |   6 +-
 target/s390x/fpu_helper.c                 |   4 +-
 target/s390x/gdbstub.c                    |  24 +--
 target/s390x/helper.c                     |   7 +-
 target/s390x/int_helper.c                 |   3 +-
 target/s390x/interrupt.c                  |   6 +-
 target/s390x/mem_helper.c                 |  30 ++--
 target/s390x/misc_helper.c                |  50 +++---
 target/s390x/mmu_helper.c                 |   8 +-
 target/s390x/sigp.c                       |   4 +-
 target/sh4/cpu.c                          |   3 +-
 target/sh4/helper.c                       |  26 ++-
 target/sh4/op_helper.c                    |  11 +-
 target/sparc/cpu.c                        |   3 +-
 target/sparc/fop_helper.c                 |   2 +-
 target/sparc/helper.c                     |   8 +-
 target/sparc/ldst_helper.c                |  33 ++--
 target/sparc/mmu_helper.c                 |  10 +-
 target/tilegx/cpu.c                       |   4 +-
 target/tilegx/helper.c                    |   2 +-
 target/tricore/cpu.c                      |   4 +-
 target/tricore/op_helper.c                |   4 +-
 target/unicore32/cpu.c                    |   3 +-
 target/unicore32/helper.c                 |   8 +-
 target/unicore32/op_helper.c              |   2 +-
 target/unicore32/softmmu.c                |  11 +-
 target/unicore32/translate.c              |  26 +--
 target/unicore32/ucf64_helper.c           |   2 +-
 target/xtensa/cpu.c                       |   3 +-
 target/xtensa/dbg_helper.c                |   4 +-
 target/xtensa/exc_helper.c                |   9 +-
 target/xtensa/helper.c                    |   2 +-
 target/xtensa/mmu_helper.c                |  11 +-
 target/xtensa/xtensa-semi.c               |   2 +-
 tcg/aarch64/tcg-target.inc.c              |  36 +---
 tcg/arm/tcg-target.inc.c                  | 149 +++++++----------
 tcg/i386/tcg-target.inc.c                 |   6 +-
 tcg/mips/tcg-target.inc.c                 |  45 +----
 tcg/ppc/tcg-target.inc.c                  |  32 +---
 tcg/riscv/tcg-target.inc.c                |  37 +----
 tcg/s390/tcg-target.inc.c                 |  13 +-
 tcg/sparc/tcg-target.inc.c                |  40 ++---
 docs/devel/tracing.txt                    |   4 +-
 scripts/tracetool/format/tcg_helper_c.py  |   2 +-
 226 files changed, 1467 insertions(+), 1912 deletions(-)
 create mode 100644 target/alpha/cpu-param.h
 create mode 100644 target/arm/cpu-param.h
 create mode 100644 target/cris/cpu-param.h
 create mode 100644 target/hppa/cpu-param.h
 create mode 100644 target/i386/cpu-param.h
 create mode 100644 target/lm32/cpu-param.h
 create mode 100644 target/m68k/cpu-param.h
 create mode 100644 target/microblaze/cpu-param.h
 create mode 100644 target/mips/cpu-param.h
 create mode 100644 target/moxie/cpu-param.h
 create mode 100644 target/nios2/cpu-param.h
 create mode 100644 target/openrisc/cpu-param.h
 create mode 100644 target/ppc/cpu-param.h
 create mode 100644 target/riscv/cpu-param.h
 create mode 100644 target/s390x/cpu-param.h
 create mode 100644 target/sh4/cpu-param.h
 create mode 100644 target/sparc/cpu-param.h
 create mode 100644 target/tilegx/cpu-param.h
 create mode 100644 target/tricore/cpu-param.h
 create mode 100644 target/unicore32/cpu-param.h
 create mode 100644 target/xtensa/cpu-param.h

-- 
2.17.1

Comments

no-reply@patchew.org March 28, 2019, 11:56 p.m. UTC | #1
Patchew URL: https://patchew.org/QEMU/20190328230404.12909-1-richard.henderson@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190328230404.12909-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH for-4.1 v2 00/36] tcg: Move the softmmu tlb to CPUNegativeOffsetState
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190328133503.6490-1-peter.maydell@linaro.org -> patchew/20190328133503.6490-1-peter.maydell@linaro.org
 t [tag update]            patchew/20190328143003.16702-1-peter.maydell@linaro.org -> patchew/20190328143003.16702-1-peter.maydell@linaro.org
 t [tag update]            patchew/20190328152635.2794-1-peter.maydell@linaro.org -> patchew/20190328152635.2794-1-peter.maydell@linaro.org
 t [tag update]            patchew/20190328152944.3199-1-peter.maydell@linaro.org -> patchew/20190328152944.3199-1-peter.maydell@linaro.org
 * [new tag]               patchew/20190328230404.12909-1-richard.henderson@linaro.org -> patchew/20190328230404.12909-1-richard.henderson@linaro.org
Auto packing the repository in background for optimum performance.
See "git help gc" for manual housekeeping.
Switched to a new branch 'test'
f9a66881e4 tcg/arm: Use LDRD to load tlb mask+table
a586dfdc11 tcg/aarch64: Use LDP to load tlb mask+table
7ef50708e7 cpu: Remove CPU_COMMON
7c6cb89b16 cpu: Move the softmmu tlb to CPUNegativeOffsetState
3543e67ac0 cpu: Move icount_decr to CPUNegativeOffsetState
113e6c106f cpu: Introduce CPUNegativeOffsetState
95d493bf38 cpu: Introduce cpu_set_cpustate_pointers
34c8a29e55 cpu: Move ENV_OFFSET to exec/gen-icount.h
dd15a5a8c7 target/xtensa: Use env_cpu, env_archcpu
a95792f513 target/unicore32: Use env_cpu, env_archcpu
5c574e3f08 target/tricore: Use env_cpu
17a6f23a59 target/tilegx: Use env_cpu
a6ab5b9053 target/sparc: Use env_cpu, env_archcpu
2818ba16bf target/sh4: Use env_cpu, env_archcpu
950b4f85e6 target/s390x: Use env_cpu, env_archcpu
ca5cfd47a6 target/riscv: Use env_cpu, env_archcpu
b66b95baa1 target/ppc: Use env_cpu, env_archcpu
ddb073ba26 target/openrisc: Use env_cpu, env_archcpu
2e474a6b7d target/nios2: Use env_cpu, env_archcpu
3825a5e3dd target/moxie: Use env_cpu, env_archcpu
0bbc8862a5 target/mips: Use env_cpu, env_archcpu
0583f518fa target/microblaze: Use env_cpu, env_archcpu
c2cf5d2738 target/m68k: Use env_cpu, env_archcpu
65f2736258 target/lm32: Use env_cpu, env_archcpu
928c5fa23c target/i386: Use env_cpu, env_archcpu
6302562a79 target/hppa: Use env_cpu, env_archcpu
745b9da831 target/cris: Use env_cpu, env_archcpu
71ddd63a36 target/arm: Use env_cpu, env_archcpu
a9d03a568d target/alpha: Use env_cpu, env_archcpu
a7dd6ee21d cpu: Introduce env_archcpu
def257dbab cpu: Replace ENV_GET_CPU with env_cpu
3f602af99d cpu: Define ArchCPU
f1145468e6 cpu: Define CPUArchState with typedef
53b9e78cca tcg: Create struct CPUTLB
73e019c8f9 tcg: Split out target/arch/cpu-param.h
2c6d24b7d4 tcg: Fold CPUTLBWindow into CPUTLBDesc

=== OUTPUT BEGIN ===
1/36 Checking commit 2c6d24b7d40f (tcg: Fold CPUTLBWindow into CPUTLBDesc)
2/36 Checking commit 73e019c8f909 (tcg: Split out target/arch/cpu-param.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56: 
new file mode 100644

WARNING: Block comments use a leading /* on a separate line
#357: FILE: target/i386/cpu-param.h:4:
+/* ??? This is really 48 bits, sign-extended, but the only thing

WARNING: Block comments use * on subsequent lines
#358: FILE: target/i386/cpu-param.h:5:
+/* ??? This is really 48 bits, sign-extended, but the only thing
+   accessible to userland with bit 48 set is the VSYSCALL, and that

WARNING: Block comments use a trailing */ on a separate line
#359: FILE: target/i386/cpu-param.h:6:
+   is handled via other mechanisms.  */

WARNING: Block comments use a leading /* on a separate line
#466: FILE: target/m68k/cpu-param.h:2:
+/* Coldfire Linux uses 8k pages

ERROR: code indent should never use tabs
#1024: FILE: target/sh4/cpu-param.h:2:
+#define TARGET_PAGE_BITS 12^I/* 4k */$

total: 1 errors, 5 warnings, 1030 lines checked

Patch 2/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/36 Checking commit 53b9e78ccaf7 (tcg: Create struct CPUTLB)
WARNING: line over 80 characters
#350: FILE: accel/tcg/cputlb.c:781:
+        env_tlb(env)->d[mmu_idx].viotlb[vidx] = env_tlb(env)->d[mmu_idx].iotlb[index];

total: 0 errors, 1 warnings, 677 lines checked

Patch 3/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/36 Checking commit f1145468e661 (cpu: Define CPUArchState with typedef)
5/36 Checking commit 3f602af99da2 (cpu: Define ArchCPU)
6/36 Checking commit def257dbabdb (cpu: Replace ENV_GET_CPU with env_cpu)
7/36 Checking commit a7dd6ee21d47 (cpu: Introduce env_archcpu)
8/36 Checking commit a9d03a568d8f (target/alpha: Use env_cpu, env_archcpu)
9/36 Checking commit 71ddd63a36f3 (target/arm: Use env_cpu, env_archcpu)
10/36 Checking commit 745b9da8311a (target/cris: Use env_cpu, env_archcpu)
ERROR: suspect code indent for conditional statements (24, 16)
#96: FILE: target/cris/op_helper.c:141:
                        if (tlb_v) {
+                tlb_flush_page(env_cpu(env), vaddr);

total: 1 errors, 0 warnings, 76 lines checked

Patch 10/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

11/36 Checking commit 6302562a7979 (target/hppa: Use env_cpu, env_archcpu)
12/36 Checking commit 928c5fa23cb7 (target/i386: Use env_cpu, env_archcpu)
13/36 Checking commit 65f273625801 (target/lm32: Use env_cpu, env_archcpu)
14/36 Checking commit c2cf5d2738d0 (target/m68k: Use env_cpu, env_archcpu)
15/36 Checking commit 0583f518fa3f (target/microblaze: Use env_cpu, env_archcpu)
16/36 Checking commit 0bbc8862a577 (target/mips: Use env_cpu, env_archcpu)
17/36 Checking commit 3825a5e3dd7f (target/moxie: Use env_cpu, env_archcpu)
18/36 Checking commit 2e474a6b7dc0 (target/nios2: Use env_cpu, env_archcpu)
19/36 Checking commit ddb073ba26a6 (target/openrisc: Use env_cpu, env_archcpu)
20/36 Checking commit b66b95baa16e (target/ppc: Use env_cpu, env_archcpu)
21/36 Checking commit ca5cfd47a6c9 (target/riscv: Use env_cpu, env_archcpu)
22/36 Checking commit 950b4f85e669 (target/s390x: Use env_cpu, env_archcpu)
23/36 Checking commit 2818ba16bff7 (target/sh4: Use env_cpu, env_archcpu)
24/36 Checking commit a6ab5b9053ed (target/sparc: Use env_cpu, env_archcpu)
25/36 Checking commit 17a6f23a59c7 (target/tilegx: Use env_cpu)
26/36 Checking commit 5c574e3f088c (target/tricore: Use env_cpu)
27/36 Checking commit a95792f513ad (target/unicore32: Use env_cpu, env_archcpu)
28/36 Checking commit dd15a5a8c7ea (target/xtensa: Use env_cpu, env_archcpu)
29/36 Checking commit 34c8a29e5557 (cpu: Move ENV_OFFSET to exec/gen-icount.h)
30/36 Checking commit 95d493bf38bd (cpu: Introduce cpu_set_cpustate_pointers)
31/36 Checking commit 113e6c106fca (cpu: Introduce CPUNegativeOffsetState)
32/36 Checking commit 3543e67ac0a3 (cpu: Move icount_decr to CPUNegativeOffsetState)
ERROR: return is not a function, parentheses are not required
#191: FILE: cpus.c:240:
+    return (cpu->icount_budget -

total: 1 errors, 0 warnings, 326 lines checked

Patch 32/36 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

33/36 Checking commit 7c6cb89b161e (cpu: Move the softmmu tlb to CPUNegativeOffsetState)
34/36 Checking commit 7ef50708e758 (cpu: Remove CPU_COMMON)
35/36 Checking commit a586dfdc11a5 (tcg/aarch64: Use LDP to load tlb mask+table)
36/36 Checking commit f9a66881e4de (tcg/arm: Use LDRD to load tlb mask+table)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190328230404.12909-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
Peter Maydell April 29, 2019, 3:12 p.m. UTC | #2
On Fri, 29 Mar 2019 at 00:44, <no-reply@patchew.org> wrote:
>

> Patchew URL: https://patchew.org/QEMU/20190328230404.12909-1-richard.henderson@linaro.org/

>

>

>

> Hi,

>

> This series seems to have some coding style problems. See output below for

> more information:


Richard -- at least some of these checkpatch nits look like
they're real rather than false positives: could you have a look
through them and fold in fixes where appropriate?

thanks
-- PMM