diff mbox series

[for-4.1,8/8] target/riscv: Remove spaces from register names

Message ID 20190401031155.21293-9-richard.henderson@linaro.org
State Superseded
Headers show
Series target/riscv: decodetree improvments | expand

Commit Message

Richard Henderson April 1, 2019, 3:11 a.m. UTC
These extra spaces make the "-d op" dump look weird.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/riscv/cpu.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

-- 
2.17.1

Comments

Palmer Dabbelt April 25, 2019, 4:04 p.m. UTC | #1
On Sun, 31 Mar 2019 20:11:55 PDT (-0700), richard.henderson@linaro.org wrote:
> These extra spaces make the "-d op" dump look weird.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/riscv/cpu.c | 16 ++++++++--------

>  1 file changed, 8 insertions(+), 8 deletions(-)

>

> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

> index d61bce6d55..624528efb5 100644

> --- a/target/riscv/cpu.c

> +++ b/target/riscv/cpu.c

> @@ -29,17 +29,17 @@

>  static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";

>

>  const char * const riscv_int_regnames[] = {

> -  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",

> -  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",

> -  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",

> -  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "

> +  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",

> +  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",

> +  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",

> +  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"

>  };

>

>  const char * const riscv_fpr_regnames[] = {

> -  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",

> -  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",

> -  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",

> -  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"

> +  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",

> +  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",

> +  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",

> +  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"

>  };

>

>  const char * const riscv_excp_names[] = {


Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d61bce6d55..624528efb5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -29,17 +29,17 @@ 
 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
 
 const char * const riscv_int_regnames[] = {
-  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",
-  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",
-  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",
-  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "
+  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
+  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
+  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
+  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
 };
 
 const char * const riscv_fpr_regnames[] = {
-  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",
-  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",
-  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",
-  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"
+  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
+  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
+  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
+  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
 };
 
 const char * const riscv_excp_names[] = {