diff mbox series

[RFC,2/3] arm_pmu: acpi: spe: Add initial MADT/SPE probing

Message ID 20190209004718.3292087-3-jeremy.linton@arm.com
State New
Headers show
Series arm64: SPE ACPI enablement | expand

Commit Message

Jeremy Linton Feb. 9, 2019, 12:47 a.m. UTC 
ACPI 6.3 adds additional fields to the MADT GICC
structure to describe SPE PPI's. We pick these out
of the cached reference to the madt_gicc structure
similarly to the core PMU code. We then create a platform
device referring to the IRQ and let the user/module loader
decide whether to load the SPE driver.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>

---
 arch/arm64/include/asm/acpi.h |  3 ++
 drivers/perf/arm_pmu_acpi.c   | 67 +++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

-- 
2.17.2

Comments

Sudeep Holla Feb. 11, 2019, 3:34 p.m. UTC | #1 
On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:
> ACPI 6.3 adds additional fields to the MADT GICC

> structure to describe SPE PPI's. We pick these out

> of the cached reference to the madt_gicc structure

> similarly to the core PMU code. We then create a platform

> device referring to the IRQ and let the user/module loader

> decide whether to load the SPE driver.

> 

> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>

> ---

>  arch/arm64/include/asm/acpi.h |  3 ++

>  drivers/perf/arm_pmu_acpi.c   | 67 +++++++++++++++++++++++++++++++++++

>  2 files changed, 70 insertions(+)

> 

> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h

> index 2def77ec14be..f9f9f2eb5d54 100644

> --- a/arch/arm64/include/asm/acpi.h

> +++ b/arch/arm64/include/asm/acpi.h

> @@ -40,6 +40,9 @@

>  	(!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \

>  	(unsigned long)(entry) + (entry)->header.length > (end))

>  

> +#define ACPI_MADT_GICC_SPE  (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \

> +	spe_overflow_interrupt) + sizeof(u16))

> +


[Nit] Does it make sense to add _OFFSET in the name ? Otherwise it may
sound like the actual interrupt number than the offset.

Other than that, this looks good to me:

Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>


Regards,
Sudeep
Jeremy Linton Feb. 14, 2019, 6:03 p.m. UTC | #2 
Hi,

Thanks for taking a look at this..

On 2/14/19 11:11 AM, Will Deacon wrote:
> Hi Jeremy,

> 

> On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:

>> ACPI 6.3 adds additional fields to the MADT GICC

>> structure to describe SPE PPI's. We pick these out

>> of the cached reference to the madt_gicc structure

>> similarly to the core PMU code. We then create a platform

>> device referring to the IRQ and let the user/module loader

>> decide whether to load the SPE driver.

>>

>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>

>> ---

>>   arch/arm64/include/asm/acpi.h |  3 ++

>>   drivers/perf/arm_pmu_acpi.c   | 67 +++++++++++++++++++++++++++++++++++

>>   2 files changed, 70 insertions(+)

>>

>> diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h

>> index 2def77ec14be..f9f9f2eb5d54 100644

>> --- a/arch/arm64/include/asm/acpi.h

>> +++ b/arch/arm64/include/asm/acpi.h

>> @@ -40,6 +40,9 @@

>>   	(!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \

>>   	(unsigned long)(entry) + (entry)->header.length > (end))

>>   

>> +#define ACPI_MADT_GICC_SPE  (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \

>> +	spe_overflow_interrupt) + sizeof(u16))

>> +

>>   /* Basic configuration for ACPI */

>>   #ifdef	CONFIG_ACPI

>>   pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);

>> diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c

>> index 0f197516d708..725d413b47dc 100644

>> --- a/drivers/perf/arm_pmu_acpi.c

>> +++ b/drivers/perf/arm_pmu_acpi.c

>> @@ -74,6 +74,71 @@ static void arm_pmu_acpi_unregister_irq(int cpu)

>>   	acpi_unregister_gsi(gsi);

>>   }

>>   

>> +static struct resource spe_resources[] = {

>> +	{

>> +		/* irq */

>> +		.flags          = IORESOURCE_IRQ,

>> +	}

>> +};

>> +

>> +static struct platform_device spe_dev = {

>> +	.name = "arm,spe-v1",

>> +	.id = -1,

>> +	.resource = spe_resources,

>> +	.num_resources = ARRAY_SIZE(spe_resources)

>> +};

>> +

>> +/*

>> + * For lack of a better place, hook the normal PMU MADT walk

>> + * and create a SPE device if we detect a recent MADT with

>> + * a homogeneous PPI mapping.

>> + */

>> +static int arm_spe_acpi_parse_irqs(void)

>> +{

>> +	int cpu, ret, irq;

>> +	u16 gsi = 0;

>> +	bool first = true;

>> +

>> +	struct acpi_madt_generic_interrupt *gicc;

>> +

>> +	/*

>> +	 * sanity check all the GICC tables for the same interrupt number

>> +	 * for now we only support homogeneous ACPI/SPE machines.

>> +	 */

>> +	for_each_possible_cpu(cpu) {

>> +		gicc = acpi_cpu_get_madt_gicc(cpu);

>> +

>> +		if (gicc->header.length < ACPI_MADT_GICC_SPE)

>> +			return -ENODEV;

>> +

>> +		if (first) {

>> +			gsi = gicc->spe_overflow_interrupt;

>> +			if (!gsi)

>> +				return -ENODEV;

>> +			first = false;

>> +		} else if (gsi != gicc->spe_overflow_interrupt) {

>> +			pr_warn("ACPI: SPE must have homogeneous interrupts\n");

>> +			return -EINVAL;

>> +		}

> 

> Unfortunately, I don't think this is sufficient to detect a homogeneous

> system: we'll have to check the MIDRs instead, which is nasty. I would

> personally be in favour of enforcing homogeneity for ACPI systems when we

> bring up secondary CPUs, but I suspect others would disagree.


Given that all the SPE capable machines i'm aware of at the moment are 
homogeneous, are we ok with just doing an online CPU MIDR check for now, 
and cleaning that up if/when someone builds a machine and complains?

Thanks,
Will Deacon Feb. 15, 2019, 3 p.m. UTC | #3 
On Thu, Feb 14, 2019 at 12:03:57PM -0600, Jeremy Linton wrote:
> On 2/14/19 11:11 AM, Will Deacon wrote:

> > On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:

> > > +/*

> > > + * For lack of a better place, hook the normal PMU MADT walk

> > > + * and create a SPE device if we detect a recent MADT with

> > > + * a homogeneous PPI mapping.

> > > + */

> > > +static int arm_spe_acpi_parse_irqs(void)

> > > +{

> > > +	int cpu, ret, irq;

> > > +	u16 gsi = 0;

> > > +	bool first = true;

> > > +

> > > +	struct acpi_madt_generic_interrupt *gicc;

> > > +

> > > +	/*

> > > +	 * sanity check all the GICC tables for the same interrupt number

> > > +	 * for now we only support homogeneous ACPI/SPE machines.

> > > +	 */

> > > +	for_each_possible_cpu(cpu) {

> > > +		gicc = acpi_cpu_get_madt_gicc(cpu);

> > > +

> > > +		if (gicc->header.length < ACPI_MADT_GICC_SPE)

> > > +			return -ENODEV;

> > > +

> > > +		if (first) {

> > > +			gsi = gicc->spe_overflow_interrupt;

> > > +			if (!gsi)

> > > +				return -ENODEV;

> > > +			first = false;

> > > +		} else if (gsi != gicc->spe_overflow_interrupt) {

> > > +			pr_warn("ACPI: SPE must have homogeneous interrupts\n");

> > > +			return -EINVAL;

> > > +		}

> > 

> > Unfortunately, I don't think this is sufficient to detect a homogeneous

> > system: we'll have to check the MIDRs instead, which is nasty. I would

> > personally be in favour of enforcing homogeneity for ACPI systems when we

> > bring up secondary CPUs, but I suspect others would disagree.

> 

> Given that all the SPE capable machines i'm aware of at the moment are

> homogeneous, are we ok with just doing an online CPU MIDR check for now, and

> cleaning that up if/when someone builds a machine and complains?


Yeah, I think we added a new bit to the PPTT to tell you that the machine is
homogenous, so just check that first and bail if it's not set.

Will
Jeremy Linton Feb. 15, 2019, 4:04 p.m. UTC | #4 
Hi,

On 2/15/19 9:00 AM, Will Deacon wrote:
> On Thu, Feb 14, 2019 at 12:03:57PM -0600, Jeremy Linton wrote:

>> On 2/14/19 11:11 AM, Will Deacon wrote:

>>> On Fri, Feb 08, 2019 at 06:47:17PM -0600, Jeremy Linton wrote:

>>>> +/*

>>>> + * For lack of a better place, hook the normal PMU MADT walk

>>>> + * and create a SPE device if we detect a recent MADT with

>>>> + * a homogeneous PPI mapping.

>>>> + */

>>>> +static int arm_spe_acpi_parse_irqs(void)

>>>> +{

>>>> +	int cpu, ret, irq;

>>>> +	u16 gsi = 0;

>>>> +	bool first = true;

>>>> +

>>>> +	struct acpi_madt_generic_interrupt *gicc;

>>>> +

>>>> +	/*

>>>> +	 * sanity check all the GICC tables for the same interrupt number

>>>> +	 * for now we only support homogeneous ACPI/SPE machines.

>>>> +	 */

>>>> +	for_each_possible_cpu(cpu) {

>>>> +		gicc = acpi_cpu_get_madt_gicc(cpu);

>>>> +

>>>> +		if (gicc->header.length < ACPI_MADT_GICC_SPE)

>>>> +			return -ENODEV;

>>>> +

>>>> +		if (first) {

>>>> +			gsi = gicc->spe_overflow_interrupt;

>>>> +			if (!gsi)

>>>> +				return -ENODEV;

>>>> +			first = false;

>>>> +		} else if (gsi != gicc->spe_overflow_interrupt) {

>>>> +			pr_warn("ACPI: SPE must have homogeneous interrupts\n");

>>>> +			return -EINVAL;

>>>> +		}

>>>

>>> Unfortunately, I don't think this is sufficient to detect a homogeneous

>>> system: we'll have to check the MIDRs instead, which is nasty. I would

>>> personally be in favour of enforcing homogeneity for ACPI systems when we

>>> bring up secondary CPUs, but I suspect others would disagree.

>>

>> Given that all the SPE capable machines i'm aware of at the moment are

>> homogeneous, are we ok with just doing an online CPU MIDR check for now, and

>> cleaning that up if/when someone builds a machine and complains?

> 

> Yeah, I think we added a new bit to the PPTT to tell you that the machine is

> homogenous, so just check that first and bail if it's not set.


Yes of course, 100% better plan. Although its probably going to have to 
be more of a case of walking all the possible cores and assuring they 
have the same flag level (similar to how the socket flag is handled). Of 
course that information is useful enough it should probably just be done 
as part of the normal cpu topology walk. Then the people who have to 
back port these patches end up with a big dependent set... <chuckle>
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 2def77ec14be..f9f9f2eb5d54 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -40,6 +40,9 @@ 
 	(!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
 	(unsigned long)(entry) + (entry)->header.length > (end))
 
+#define ACPI_MADT_GICC_SPE  (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \
+	spe_overflow_interrupt) + sizeof(u16))
+
 /* Basic configuration for ACPI */
 #ifdef	CONFIG_ACPI
 pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
index 0f197516d708..725d413b47dc 100644
--- a/drivers/perf/arm_pmu_acpi.c
+++ b/drivers/perf/arm_pmu_acpi.c
@@ -74,6 +74,71 @@  static void arm_pmu_acpi_unregister_irq(int cpu)
 	acpi_unregister_gsi(gsi);
 }
 
+static struct resource spe_resources[] = {
+	{
+		/* irq */
+		.flags          = IORESOURCE_IRQ,
+	}
+};
+
+static struct platform_device spe_dev = {
+	.name = "arm,spe-v1",
+	.id = -1,
+	.resource = spe_resources,
+	.num_resources = ARRAY_SIZE(spe_resources)
+};
+
+/*
+ * For lack of a better place, hook the normal PMU MADT walk
+ * and create a SPE device if we detect a recent MADT with
+ * a homogeneous PPI mapping.
+ */
+static int arm_spe_acpi_parse_irqs(void)
+{
+	int cpu, ret, irq;
+	u16 gsi = 0;
+	bool first = true;
+
+	struct acpi_madt_generic_interrupt *gicc;
+
+	/*
+	 * sanity check all the GICC tables for the same interrupt number
+	 * for now we only support homogeneous ACPI/SPE machines.
+	 */
+	for_each_possible_cpu(cpu) {
+		gicc = acpi_cpu_get_madt_gicc(cpu);
+
+		if (gicc->header.length < ACPI_MADT_GICC_SPE)
+			return -ENODEV;
+
+		if (first) {
+			gsi = gicc->spe_overflow_interrupt;
+			if (!gsi)
+				return -ENODEV;
+			first = false;
+		} else if (gsi != gicc->spe_overflow_interrupt) {
+			pr_warn("ACPI: SPE must have homogeneous interrupts\n");
+			return -EINVAL;
+		}
+	}
+
+	irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
+				ACPI_ACTIVE_HIGH);
+	if (irq < 0) {
+		pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
+		return irq;
+	}
+
+	spe_resources[0].start = irq;
+	ret = platform_device_register(&spe_dev);
+	if (ret < 0) {
+		pr_warn("ACPI: SPE: Unable to register device\n");
+		acpi_unregister_gsi(gsi);
+	}
+
+	return ret;
+}
+
 static int arm_pmu_acpi_parse_irqs(void)
 {
 	int irq, cpu, irq_cpu, err;
@@ -279,6 +344,8 @@  static int arm_pmu_acpi_init(void)
 	if (acpi_disabled)
 		return 0;
 
+	arm_spe_acpi_parse_irqs(); /* failures are expected */
+
 	ret = arm_pmu_acpi_parse_irqs();
 	if (ret)
 		return ret;