Message ID | 20181207170951.7307-1-richard.henderson@linaro.org |
---|---|
State | New |
Headers | show |
Series | target/i386: Generate #UD when applying LOCK to a register | expand |
Cc'ing Alberto On 12/7/18 6:09 PM, Richard Henderson wrote: > This covers inc, dec, and the bit test instructions. > > I believe we've finally covered all of the cases for > which we have an atomic path that would use the cpu_A0 > temp, which is only initialized for address sources. > Reported-by: Alberto Ortega <aortega.lms@gmail.com> > Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/translate.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/target/i386/translate.c b/target/i386/translate.c > index 0dd5fbe45c..eb52322a47 100644 > --- a/target/i386/translate.c > +++ b/target/i386/translate.c > @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) > static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) > { > if (s1->prefix & PREFIX_LOCK) { > + if (d != OR_TMP0) { > + /* Lock prefix when destination is not memory. */ > + gen_illegal_opcode(s1); > + return; > + } > tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); > tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, > s1->mem_index, ot | MO_LE); > @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > /* load shift */ > @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > bt_op: >
Ping. On 12/7/18 5:09 PM, Richard Henderson wrote: > This covers inc, dec, and the bit test instructions. > > I believe we've finally covered all of the cases for > which we have an atomic path that would use the cpu_A0 > temp, which is only initialized for address sources. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/translate.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/target/i386/translate.c b/target/i386/translate.c > index 0dd5fbe45c..eb52322a47 100644 > --- a/target/i386/translate.c > +++ b/target/i386/translate.c > @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) > static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) > { > if (s1->prefix & PREFIX_LOCK) { > + if (d != OR_TMP0) { > + /* Lock prefix when destination is not memory. */ > + gen_illegal_opcode(s1); > + return; > + } > tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); > tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, > s1->mem_index, ot | MO_LE); > @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > /* load shift */ > @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > bt_op: >
On 2/6/19 6:42 AM, Richard Henderson wrote: > Ping. > > On 12/7/18 5:09 PM, Richard Henderson wrote: >> This covers inc, dec, and the bit test instructions. >> >> I believe we've finally covered all of the cases for >> which we have an atomic path that would use the cpu_A0 >> temp, which is only initialized for address sources. >> >> Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 Reported-by: Alberto Ortega <aortega.lms@gmail.com> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> >> --- >> target/i386/translate.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/target/i386/translate.c b/target/i386/translate.c >> index 0dd5fbe45c..eb52322a47 100644 >> --- a/target/i386/translate.c >> +++ b/target/i386/translate.c >> @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) >> static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) >> { >> if (s1->prefix & PREFIX_LOCK) { >> + if (d != OR_TMP0) { >> + /* Lock prefix when destination is not memory. */ >> + gen_illegal_opcode(s1); >> + return; >> + } >> tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); >> tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, >> s1->mem_index, ot | MO_LE); >> @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) >> gen_op_ld_v(s, ot, s->T0, s->A0); >> } >> } else { >> + if (s->prefix & PREFIX_LOCK) { >> + goto illegal_op; >> + } >> gen_op_mov_v_reg(s, ot, s->T0, rm); >> } >> /* load shift */ >> @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) >> gen_op_ld_v(s, ot, s->T0, s->A0); >> } >> } else { >> + if (s->prefix & PREFIX_LOCK) { >> + goto illegal_op; >> + } >> gen_op_mov_v_reg(s, ot, s->T0, rm); >> } >> bt_op: >> > >
On 07/12/18 18:09, Richard Henderson wrote: > This covers inc, dec, and the bit test instructions. > > I believe we've finally covered all of the cases for > which we have an atomic path that would use the cpu_A0 > temp, which is only initialized for address sources. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/i386/translate.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/target/i386/translate.c b/target/i386/translate.c > index 0dd5fbe45c..eb52322a47 100644 > --- a/target/i386/translate.c > +++ b/target/i386/translate.c > @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) > static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) > { > if (s1->prefix & PREFIX_LOCK) { > + if (d != OR_TMP0) { > + /* Lock prefix when destination is not memory. */ > + gen_illegal_opcode(s1); > + return; > + } > tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); > tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, > s1->mem_index, ot | MO_LE); > @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > /* load shift */ > @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) > gen_op_ld_v(s, ot, s->T0, s->A0); > } > } else { > + if (s->prefix & PREFIX_LOCK) { > + goto illegal_op; > + } > gen_op_mov_v_reg(s, ot, s->T0, rm); > } > bt_op: > Queued, thanks. Paolo
diff --git a/target/i386/translate.c b/target/i386/translate.c index 0dd5fbe45c..eb52322a47 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) { if (s1->prefix & PREFIX_LOCK) { + if (d != OR_TMP0) { + /* Lock prefix when destination is not memory. */ + gen_illegal_opcode(s1); + return; + } tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1); tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, s1->mem_index, ot | MO_LE); @@ -6764,6 +6769,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_op_ld_v(s, ot, s->T0, s->A0); } } else { + if (s->prefix & PREFIX_LOCK) { + goto illegal_op; + } gen_op_mov_v_reg(s, ot, s->T0, rm); } /* load shift */ @@ -6803,6 +6811,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_op_ld_v(s, ot, s->T0, s->A0); } } else { + if (s->prefix & PREFIX_LOCK) { + goto illegal_op; + } gen_op_mov_v_reg(s, ot, s->T0, rm); } bt_op:
This covers inc, dec, and the bit test instructions. I believe we've finally covered all of the cases for which we have an atomic path that would use the cpu_A0 temp, which is only initialized for address sources. Fixes: https://bugs.launchpad.net/qemu/+bug/1803160/comments/4 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/i386/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.2