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[00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC

Message ID 20190114132424.6445-1-kishon@ti.com
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Series Add support for PCIe RC and EP mode in TI's AM654 SoC | expand

Message

Kishon Vijay Abraham I Jan. 14, 2019, 1:24 p.m. UTC
Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
uses Synopsys core revision 4.90a and uses the same TI wrapper as used
in keystone2 with certain modification. Hence AM654 will use the same
pci wrapper driver pci-keystone.c

This series was initially part of [1]. This series only includes patches
that has to be merged via Lorenzo's tree. The PHY patches and dt patches
will be sent separately.

This series is created over my keystone MSI cleanup series [2] and EPC
features series [3].

This series:
*) Cleanup pci-keystone driver so that both RC mode and EP mode of
   AM654 can be supported
*) Modify epc-core to support allocation of aligned buffers required for
   AM654
*) Fix ATU unroll identification
*) Add support for both host mode and device mode in AM654    

[1] -> https://lore.kernel.org/patchwork/cover/989487/
[2] -> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1883081.html
[3] -> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1899011.html

Kishon Vijay Abraham I (24):
  PCI: keystone: Add start_link/stop_link dw_pcie_ops
  PCI: keystone: Cleanup error_irq configuration
  dt-bindings: PCI: keystone: Add "reg-names" binding information
  PCI: keystone: Perform host initialization in a single function
  PCI: keystone: Use platform_get_resource_byname to get memory
    resources
  PCI: keystone: Move initializations to appropriate places
  dt-bindings: PCI: Add dt-binding to configure PCIe mode
  PCI: keystone: Explicitly set the PCIe mode
  dt-bindings: PCI: Document "atu" reg-names
  PCI: dwc: Enable iATU unroll for endpoint too
  PCI: dwc: Fix ATU identification for designware version >= 4.80
  PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
  dt-bindings: PCI: Add PCI RC dt binding documentation for AM654
  PCI: keystone: Add support for PCIe RC in AM654x Platforms
  PCI: keystone: Invoke phy_reset API before enabling PHY
  PCI: endpoint: Add support to allocate aligned buffers to be mapped in
    BARs
  PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
  PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability
    offset
  PCI: dwc: Add callbacks for accessing dbi2 address space
  PCI: keystone: Add support for PCIe EP in AM654x Platforms
  PCI: designware-ep: Configure RESBAR to advertise the smallest size
  PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
  misc: pci_endpoint_test: Add support to test PCI EP in AM654x
  misc: pci_endpoint_test: Fix test_reg_bar to be updated in
    pci_endpoint_test

 .../bindings/pci/designware-pcie.txt          |   7 +-
 .../devicetree/bindings/pci/pci-keystone.txt  |  14 +-
 drivers/misc/pci_endpoint_test.c              |  17 +
 drivers/pci/controller/dwc/Kconfig            |  25 +-
 drivers/pci/controller/dwc/pci-dra7xx.c       |   2 +-
 drivers/pci/controller/dwc/pci-keystone.c     | 505 ++++++++++++++----
 drivers/pci/controller/dwc/pcie-artpec6.c     |   2 +-
 .../pci/controller/dwc/pcie-designware-ep.c   |  55 +-
 .../pci/controller/dwc/pcie-designware-host.c |  19 -
 .../pci/controller/dwc/pcie-designware-plat.c |   2 +-
 drivers/pci/controller/dwc/pcie-designware.c  |  52 ++
 drivers/pci/controller/dwc/pcie-designware.h  |  15 +-
 drivers/pci/endpoint/functions/pci-epf-test.c |   5 +-
 drivers/pci/endpoint/pci-epf-core.c           |  10 +-
 include/linux/pci-epc.h                       |   2 +
 include/linux/pci-epf.h                       |   3 +-
 16 files changed, 587 insertions(+), 148 deletions(-)

-- 
2.17.1

Comments

Rob Herring (Arm) Jan. 22, 2019, 12:31 a.m. UTC | #1
On Mon, 14 Jan 2019 18:54:03 +0530, Kishon Vijay Abraham I wrote:
> Add "reg-names" binding information in order for device tree node

> to be populated with the correct register strings. This will break

> old dt compatibility. However Keystone PCI has never worked

> in upstream kernel due to lack of SERDES support. Before SERDES

> support is added, cleanup the Keystone PCI dt-bindngs. This new

> binding will also be used by PCI in AM654 platform.

> 

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

> ---

>  Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++--

>  1 file changed, 4 insertions(+), 2 deletions(-)

> 


Reviewed-by: Rob Herring <robh@kernel.org>
Rob Herring (Arm) Jan. 22, 2019, 12:48 a.m. UTC | #2
On Mon, Jan 14, 2019 at 06:54:09PM +0530, Kishon Vijay Abraham I wrote:
> Document "atu" reg-names required to get the register space for ATU in

> Synopsys designware core version >= 4.80.

> 

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

> ---

>  Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++--

>  1 file changed, 5 insertions(+), 2 deletions(-)

> 

> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt

> index c124f9bc11f3..5561a1c060d0 100644

> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt

> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt

> @@ -4,8 +4,11 @@ Required properties:

>  - compatible:

>  	"snps,dw-pcie" for RC mode;

>  	"snps,dw-pcie-ep" for EP mode;

> -- reg: Should contain the configuration address space.

> -- reg-names: Must be "config" for the PCIe configuration space.

> +- reg: For designware cores version < 4.80 contains the configuration

> +       address space. For designware core version >= 4.80, contains

> +       the configuration and ATU address space

> +- reg-names: Must be "config" for the PCIe configuration space and "atu" for

> +	     the ATU address space.


I'm pretty sure we already have other platforms with an ATU. Those all 
just represent it with the other ctrl registers? So maybe this is TI 
specific that it is separate. Or should have some conditional like 'if 
the ATU space is separate, the reg-name should be atu'.

>      (The old way of getting the configuration address space from "ranges"

>      is deprecated and should be avoided.)

>  - num-lanes: number of lanes to use

> -- 

> 2.17.1

>
Rob Herring (Arm) Jan. 22, 2019, 12:48 a.m. UTC | #3
On Mon, 14 Jan 2019 18:54:13 +0530, Kishon Vijay Abraham I wrote:
> Add devicetree binding documentation for PCIe in RC mode present in

> AM654 SoC.

> 

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

> ---

>  Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++-

>  1 file changed, 5 insertions(+), 1 deletion(-)

> 


Reviewed-by: Rob Herring <robh@kernel.org>