| Message ID | 20181219124207.13479-8-kishon@ti.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: DWC/Keystone: MSI configuration cleanup | expand |
Hi, On 19/12/2018 12:42, Kishon Vijay Abraham I wrote: > Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for > configuring the MSI controller logic within the Designware IP. However > certain platforms like Keystone (K2G) which uses Desingware IP has > it's own MSI controller logic. For handling such platforms, > the irqchip ops uses msi_irq_ack, msi_set_irq, msi_clear_irq callback > functions. Keystone also uses get_msi_addr and get_msi_data callbacks, do you want to update the description to add those references as well? > > Add support to use different msi_irq_chip with default as > dw_pci_msi_bottom_irq_chip. This is in preparation to get rid off > msi_irq_ack, msi_set_irq, msi_clear_irq and other Keystone specific > dw_pcie_host_ops. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 0fa9e8fdce66..db21bd11f153 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, > > for (i = 0; i < nr_irqs; i++) > irq_domain_set_info(domain, virq + i, bit + i, > - &dw_pci_msi_bottom_irq_chip, > + pp->msi_irq_chip, > pp, handle_edge_irq, > NULL, NULL); > > @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); > > + if (!pp->msi_irq_chip) > + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; > + > pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, > &dw_pcie_msi_domain_ops, pp); > if (!pp->irq_domain) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 0989d880ac46..0873ee4084aa 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -168,6 +168,7 @@ struct pcie_port { > struct irq_domain *irq_domain; > struct irq_domain *msi_domain; > dma_addr_t msi_data; > + struct irq_chip *msi_irq_chip; > u32 num_vectors; > u32 irq_status[MAX_MSI_CTRLS]; > raw_spinlock_t lock; > Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Regards, Gustavo
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0fa9e8fdce66..db21bd11f153 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0989d880ac46..0873ee4084aa 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -168,6 +168,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock;
Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the Designware IP. However certain platforms like Keystone (K2G) which uses Desingware IP has it's own MSI controller logic. For handling such platforms, the irqchip ops uses msi_irq_ack, msi_set_irq, msi_clear_irq callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid off msi_irq_ack, msi_set_irq, msi_clear_irq and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1