diff mbox series

[edk2,v3,06/16] ArmPkg/ArmLib: add support for reading the max physical address space size

Message ID 20181128143357.991-7-ard.biesheuvel@linaro.org
State Accepted
Commit 95d04ebca8be8f71a23e85a2f4822ba90a2e32cc
Headers show
Series Pkg: lift 40-bit IPA space limit | expand

Commit Message

Ard Biesheuvel Nov. 28, 2018, 2:33 p.m. UTC 
Add a helper function that returns the maximum physical address space
size as supported by the current CPU.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

---
 ArmPkg/Include/Library/ArmLib.h               |  6 ++++++
 ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++
 ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S     |  8 ++++++++
 ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm   |  8 ++++++++
 4 files changed, 39 insertions(+)

-- 
2.19.1

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Comments

Philippe Mathieu-Daudé Nov. 28, 2018, 2:41 p.m. UTC | #1 
On 28/11/18 15:33, Ard Biesheuvel wrote:
> Add a helper function that returns the maximum physical address space
> size as supported by the current CPU.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  ArmPkg/Include/Library/ArmLib.h               |  6 ++++++
>  ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++
>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S     |  8 ++++++++
>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm   |  8 ++++++++
>  4 files changed, 39 insertions(+)
> 
> diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
> index ffda50e9d767..9a804c15fdb6 100644
> --- a/ArmPkg/Include/Library/ArmLib.h
> +++ b/ArmPkg/Include/Library/ArmLib.h
> @@ -733,4 +733,10 @@ ArmWriteCntvOff (
>    UINT64   Val
>    );
>  
> +UINTN
> +EFIAPI
> +ArmGetPhysicalAddressBits (
> +  VOID
> +  );
> +
>  #endif // __ARM_LIB__
> diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> index 1ef2f61f5979..b7173e00b039 100644
> --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
> @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr)
>  3:msr   sctlr_el3, x0
>  4:ret
>  
> +ASM_FUNC(ArmGetPhysicalAddressBits)
> +  mrs   x0, id_aa64mmfr0_el1
> +  adr   x1, .LPARanges
> +  and   x0, x0, #0xf
> +  ldrb  w0, [x1, x0]
> +  ret
> +
> +//
> +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
> +// physical address space support on this CPU:
> +// 0 == 32 bits, 1 == 36 bits, etc etc
> +// 7 and up are reserved
> +//
> +.LPARanges:
> +  .byte 32, 36, 40, 42, 44, 48, 52,  0
> +  .byte  0,  0,  0,  0,  0,  0,  0,  0
> +
>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
> index f2a517671f0a..0e9f9d0453e4 100644
> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
> @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr)
>    isb
>    bx      lr
>  
> +ASM_FUNC (ArmGetPhysicalAddressBits)
> +  mrc     p15, 0, r0, c0, c1, 4   // MMFR0
> +  and     r0, r0, #0xf            // VMSA [3:0]
> +  cmp     r0, #5                  // >= 5 implies LPAE support
> +  movlt   r0, #32                 // 32 bits if no LPAE
> +  movge   r0, #40                 // 40 bits if LPAE
> +  bx      lr
> +
>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
> index 219140c22b13..3eb52875971d 100644
> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
> @@ -169,4 +169,12 @@
>    isb
>    bx      lr
>  
> + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits
> +  mrc     p15, 0, r0, c0, c1, 4   ; MMFR0
> +  and     r0, r0, #0xf            ; VMSA [3:0]
> +  cmp     r0, #5                  ; >= 5 implies LPAE support
> +  movlt   r0, #32                 ; 32 bits if no LPAE
> +  movge   r0, #40                 ; 40 bits if LPAE
> +  bx      lr
> +
>    END
>
Laszlo Ersek Nov. 28, 2018, 6:44 p.m. UTC | #2 
On 11/28/18 15:33, Ard Biesheuvel wrote:
> Add a helper function that returns the maximum physical address space

> size as supported by the current CPU.

> 

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

> ---

>  ArmPkg/Include/Library/ArmLib.h               |  6 ++++++

>  ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++

>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S     |  8 ++++++++

>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm   |  8 ++++++++

>  4 files changed, 39 insertions(+)

> 

> diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h

> index ffda50e9d767..9a804c15fdb6 100644

> --- a/ArmPkg/Include/Library/ArmLib.h

> +++ b/ArmPkg/Include/Library/ArmLib.h

> @@ -733,4 +733,10 @@ ArmWriteCntvOff (

>    UINT64   Val

>    );

>  

> +UINTN

> +EFIAPI

> +ArmGetPhysicalAddressBits (

> +  VOID

> +  );

> +

>  #endif // __ARM_LIB__

> diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> index 1ef2f61f5979..b7173e00b039 100644

> --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr)

>  3:msr   sctlr_el3, x0

>  4:ret

>  

> +ASM_FUNC(ArmGetPhysicalAddressBits)

> +  mrs   x0, id_aa64mmfr0_el1

> +  adr   x1, .LPARanges

> +  and   x0, x0, #0xf

> +  ldrb  w0, [x1, x0]

> +  ret

> +

> +//

> +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the

> +// physical address space support on this CPU:

> +// 0 == 32 bits, 1 == 36 bits, etc etc

> +// 7 and up are reserved

> +//

> +.LPARanges:

> +  .byte 32, 36, 40, 42, 44, 48, 52,  0

> +  .byte  0,  0,  0,  0,  0,  0,  0,  0

> +

>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> index f2a517671f0a..0e9f9d0453e4 100644

> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr)

>    isb

>    bx      lr

>  

> +ASM_FUNC (ArmGetPhysicalAddressBits)

> +  mrc     p15, 0, r0, c0, c1, 4   // MMFR0

> +  and     r0, r0, #0xf            // VMSA [3:0]

> +  cmp     r0, #5                  // >= 5 implies LPAE support

> +  movlt   r0, #32                 // 32 bits if no LPAE

> +  movge   r0, #40                 // 40 bits if LPAE

> +  bx      lr

> +

>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> index 219140c22b13..3eb52875971d 100644

> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> @@ -169,4 +169,12 @@

>    isb

>    bx      lr

>  

> + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits

> +  mrc     p15, 0, r0, c0, c1, 4   ; MMFR0

> +  and     r0, r0, #0xf            ; VMSA [3:0]

> +  cmp     r0, #5                  ; >= 5 implies LPAE support

> +  movlt   r0, #32                 ; 32 bits if no LPAE

> +  movge   r0, #40                 ; 40 bits if LPAE

> +  bx      lr

> +

>    END

> 


I didn't review the assembly code, but formally, the patch looks OK to me.

Acked-by: Laszlo Ersek <lersek@redhat.com>

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Leif Lindholm Nov. 29, 2018, 3:42 p.m. UTC | #3 
On Wed, Nov 28, 2018 at 03:33:47PM +0100, Ard Biesheuvel wrote:
> Add a helper function that returns the maximum physical address space

> size as supported by the current CPU.

> 

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>


> ---

>  ArmPkg/Include/Library/ArmLib.h               |  6 ++++++

>  ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++

>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S     |  8 ++++++++

>  ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm   |  8 ++++++++

>  4 files changed, 39 insertions(+)

> 

> diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h

> index ffda50e9d767..9a804c15fdb6 100644

> --- a/ArmPkg/Include/Library/ArmLib.h

> +++ b/ArmPkg/Include/Library/ArmLib.h

> @@ -733,4 +733,10 @@ ArmWriteCntvOff (

>    UINT64   Val

>    );

>  

> +UINTN

> +EFIAPI

> +ArmGetPhysicalAddressBits (

> +  VOID

> +  );

> +

>  #endif // __ARM_LIB__

> diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> index 1ef2f61f5979..b7173e00b039 100644

> --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S

> @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr)

>  3:msr   sctlr_el3, x0

>  4:ret

>  

> +ASM_FUNC(ArmGetPhysicalAddressBits)

> +  mrs   x0, id_aa64mmfr0_el1

> +  adr   x1, .LPARanges

> +  and   x0, x0, #0xf

> +  ldrb  w0, [x1, x0]

> +  ret

> +

> +//

> +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the

> +// physical address space support on this CPU:

> +// 0 == 32 bits, 1 == 36 bits, etc etc

> +// 7 and up are reserved

> +//

> +.LPARanges:

> +  .byte 32, 36, 40, 42, 44, 48, 52,  0

> +  .byte  0,  0,  0,  0,  0,  0,  0,  0

> +

>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> index f2a517671f0a..0e9f9d0453e4 100644

> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

> @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr)

>    isb

>    bx      lr

>  

> +ASM_FUNC (ArmGetPhysicalAddressBits)

> +  mrc     p15, 0, r0, c0, c1, 4   // MMFR0

> +  and     r0, r0, #0xf            // VMSA [3:0]

> +  cmp     r0, #5                  // >= 5 implies LPAE support

> +  movlt   r0, #32                 // 32 bits if no LPAE

> +  movge   r0, #40                 // 40 bits if LPAE

> +  bx      lr

> +

>  ASM_FUNCTION_REMOVE_IF_UNREFERENCED

> diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> index 219140c22b13..3eb52875971d 100644

> --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm

> @@ -169,4 +169,12 @@

>    isb

>    bx      lr

>  

> + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits

> +  mrc     p15, 0, r0, c0, c1, 4   ; MMFR0

> +  and     r0, r0, #0xf            ; VMSA [3:0]

> +  cmp     r0, #5                  ; >= 5 implies LPAE support

> +  movlt   r0, #32                 ; 32 bits if no LPAE

> +  movge   r0, #40                 ; 40 bits if LPAE

> +  bx      lr

> +

>    END

> -- 

> 2.19.1

> 

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diff mbox series

Patch

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index ffda50e9d767..9a804c15fdb6 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -733,4 +733,10 @@  ArmWriteCntvOff (
   UINT64   Val
   );
 
+UINTN
+EFIAPI
+ArmGetPhysicalAddressBits (
+  VOID
+  );
+
 #endif // __ARM_LIB__
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index 1ef2f61f5979..b7173e00b039 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -196,4 +196,21 @@  ASM_FUNC(ArmWriteSctlr)
 3:msr   sctlr_el3, x0
 4:ret
 
+ASM_FUNC(ArmGetPhysicalAddressBits)
+  mrs   x0, id_aa64mmfr0_el1
+  adr   x1, .LPARanges
+  and   x0, x0, #0xf
+  ldrb  w0, [x1, x0]
+  ret
+
+//
+// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
+// physical address space support on this CPU:
+// 0 == 32 bits, 1 == 36 bits, etc etc
+// 7 and up are reserved
+//
+.LPARanges:
+  .byte 32, 36, 40, 42, 44, 48, 52,  0
+  .byte  0,  0,  0,  0,  0,  0,  0,  0
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
index f2a517671f0a..0e9f9d0453e4 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
@@ -165,4 +165,12 @@  ASM_FUNC(ArmWriteCpuActlr)
   isb
   bx      lr
 
+ASM_FUNC (ArmGetPhysicalAddressBits)
+  mrc     p15, 0, r0, c0, c1, 4   // MMFR0
+  and     r0, r0, #0xf            // VMSA [3:0]
+  cmp     r0, #5                  // >= 5 implies LPAE support
+  movlt   r0, #32                 // 32 bits if no LPAE
+  movge   r0, #40                 // 40 bits if LPAE
+  bx      lr
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
index 219140c22b13..3eb52875971d 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
@@ -169,4 +169,12 @@ 
   isb
   bx      lr
 
+ RVCT_ASM_EXPORT ArmGetPhysicalAddressBits
+  mrc     p15, 0, r0, c0, c1, 4   ; MMFR0
+  and     r0, r0, #0xf            ; VMSA [3:0]
+  cmp     r0, #5                  ; >= 5 implies LPAE support
+  movlt   r0, #32                 ; 32 bits if no LPAE
+  movge   r0, #40                 ; 40 bits if LPAE
+  bx      lr
+
   END