diff mbox series

[v2] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2

Message ID 20180903095235.13853-1-kishon@ti.com
State Superseded
Headers show
Series [v2] arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2 | expand

Commit Message

Kishon Vijay Abraham I Sept. 3, 2018, 9:52 a.m. UTC 
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
register space. The size of the address space above the 4GB SoC address
space is 4GB. These address ranges will be used by CPU/DMA to access
the PCIe address space. In order to represent the address space above
the 4GB SoC address space and to represent the size of this address
space as 4GB, change address-cells and size-cells of interconnect to 2.

Since OSPI has similar need in MCU Domain Memory Map, change
address-cells and size-cells of cbass_mcu interconnect also to 2.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

---
Changes from v1:
Changed address-cells and size-cells of cbass_mcu to "2" since OSPI has
a region of size 4GB above the 4GB space.
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 10 +++---
 arch/arm64/boot/dts/ti/k3-am65.dtsi      | 44 ++++++++++++------------
 2 files changed, 27 insertions(+), 27 deletions(-)

-- 
2.17.1

Comments

Tony Lindgren Sept. 4, 2018, 3:14 p.m. UTC | #1 
* Kishon Vijay Abraham I <kishon@ti.com> [180903 09:56]:
> AM65 has two PCIe controllers and each PCIe controller has '2' address

> spaces one within the 4GB address space of the SoC and the other above

> the 4GB address space of the SoC (cbass_main) in addition to the

> register space. The size of the address space above the 4GB SoC address

> space is 4GB. These address ranges will be used by CPU/DMA to access

> the PCIe address space. In order to represent the address space above

> the 4GB SoC address space and to represent the size of this address

> space as 4GB, change address-cells and size-cells of interconnect to 2.

> 

> Since OSPI has similar need in MCU Domain Memory Map, change

> address-cells and size-cells of cbass_mcu interconnect also to 2.

> 

> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

> ---

> Changes from v1:

> Changed address-cells and size-cells of cbass_mcu to "2" since OSPI has

> a region of size 4GB above the 4GB space.



Acked-by: Tony Lindgren <tony@atomide.com>
Vignesh Raghavendra Sept. 4, 2018, 3:22 p.m. UTC | #2 
On Tuesday 04 September 2018 07:11 PM, Menon, Nishanth wrote:
> On 15:22-20180903, Kishon Vijay Abraham I wrote:

> 

>> AM65 has two PCIe controllers and each PCIe controller has '2' address

>> spaces one within the 4GB address space of the SoC and the other above

>> the 4GB address space of the SoC (cbass_main) in addition to the

>> register space. The size of the address space above the 4GB SoC address

>> space is 4GB. These address ranges will be used by CPU/DMA to access

>> the PCIe address space. In order to represent the address space above

>> the 4GB SoC address space and to represent the size of this address

>> space as 4GB, change address-cells and size-cells of interconnect to 2.

>>

>> Since OSPI has similar need in MCU Domain Memory Map, change

>> address-cells and size-cells of cbass_mcu interconnect also to 2.

>>

> 

> Please add Fixes

> 

> Vignesh, Sekhar, Tony,

> 

> Do we agree this is the right way to go forward? if yes, please

> ack.

> 

>


LGTM, thanks kishon!

Acked-by: Vignesh R <vigneshr@ti.com>




-- 
Regards
Vignesh
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 2409344df4fa..faace3805c01 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -8,13 +8,13 @@ 
 &cbass_main {
 	gic500: interrupt-controller@1800000 {
 		compatible = "arm,gic-v3";
-		#address-cells = <1>;
-		#size-cells = <1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
 		ranges;
 		#interrupt-cells = <3>;
 		interrupt-controller;
-		reg = <0x01800000 0x10000>,	/* GICD */
-		      <0x01880000 0x90000>;	/* GICR */
+		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
+		      <0x00 0x01880000 0x00 0x90000>;	/* GICR */
 		/*
 		 * vcpumntirq:
 		 * virtual CPU interface maintenance interrupt
@@ -23,7 +23,7 @@ 
 
 		gic_its: gic-its@18200000 {
 			compatible = "arm,gic-v3-its";
-			reg = <0x01820000 0x10000>;
+			reg = <0x00 0x01820000 0x00 0x10000>;
 			msi-controller;
 			#msi-cells = <1>;
 		};
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index cede1fa0983c..ded364d20835 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -46,38 +46,38 @@ 
 
 	cbass_main: interconnect@100000 {
 		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
-			 <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
-			 <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
-			 <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
-			 <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
+			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
 			 /* MCUSS Range */
-			 <0x28380000 0x00 0x28380000 0x03880000>,
-			 <0x40200000 0x00 0x40200000 0x00900100>,
-			 <0x42040000 0x00 0x42040000 0x03ac2400>,
-			 <0x45100000 0x00 0x45100000 0x00c24000>,
-			 <0x46000000 0x00 0x46000000 0x00200000>,
-			 <0x47000000 0x00 0x47000000 0x00068400>;
+			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
 
 		cbass_mcu: interconnect@28380000 {
 			compatible = "simple-bus";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
-				 <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
-				 <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
-				 <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
-				 <0x46000000 0x46000000 0x00200000>, /* CPSW */
-				 <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
+				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
 
 			cbass_wakeup: interconnect@42040000 {
 				compatible = "simple-bus";
 				#address-cells = <1>;
 				#size-cells = <1>;
 				/* WKUP  Basic peripherals */
-				ranges = <0x42040000 0x42040000 0x03ac2400>;
+				ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
 			};
 		};
 	};