| Message ID | 20180828102642.26482-1-kishon@ti.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2 | expand |
* Kishon Vijay Abraham I <kishon@ti.com> [180828 10:31]: > AM65 has two PCIe controllers and each PCIe controller has '2' address > spaces one within the 4GB address space of the SoC and the other above > the 4GB address space of the SoC in addition to the register space. The > size of the address space above the 4GB SoC address space is 4GB. These > address ranges will be used by CPU/DMA to access the PCIe address space. > In order to represent the address space above the 4GB SoC address space > and to represent the size of this address space as 4GB, change > address-cells and size-cells of interconnect to 2. ... > cbass_mcu: interconnect@28380000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; Yup great, the interconnect instances that don't need above 4GB address space should stay this way. Acked-by: Tony Lindgren <tony@atomide.com>
Kishon, On 28-Aug-18 9:55 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I <kishon@ti.com> [180828 10:31]: >> AM65 has two PCIe controllers and each PCIe controller has '2' address >> spaces one within the 4GB address space of the SoC and the other above >> the 4GB address space of the SoC in addition to the register space. The >> size of the address space above the 4GB SoC address space is 4GB. These >> address ranges will be used by CPU/DMA to access the PCIe address space. >> In order to represent the address space above the 4GB SoC address space >> and to represent the size of this address space as 4GB, change >> address-cells and size-cells of interconnect to 2. > ... >> cbass_mcu: interconnect@28380000 { >> compatible = "simple-bus"; >> #address-cells = <1>; >> #size-cells = <1>; > Looking at Table 2-2. MCU Domain Memory Map in TRM, OSPI has similar need. There are two address ranges to access OSPI flash in memory mapped mode: MCU_FSS0_DAT_REG1 0x0050000000 0x0058000000 128 MB(32bit space) MCU_FSS0_DAT_REG0 0x0400000000 0x0500000000 4 GB(64bit space with ECC) MCU_FSS0_DAT_REG3 0x0500000000 0x0600000000 4 GB(64bit space w/o ECC) Since, there are already OSPI flashes with size > 128MB, we would need to use 4GB address space in kernel (which is above 32 bit space) Therefore, could you also change cbass_mcu also to have #address-cells = <2>? Regards Vignesh
On 15:56-20180828, Kishon Vijay Abraham I wrote: [...] > cbass_mcu: interconnect@28380000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ > - <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ > - <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ > - <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ > - <0x46000000 0x46000000 0x00200000>, /* CPSW */ > - <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ > + ranges = <0x28380000 0x00 0x28380000 0x03880000>, /* MCU NAVSS*/ > + <0x40200000 0x00 0x40200000 0x00900100>, /* First peripheral window */ > + <0x42040000 0x00 0x42040000 0x03ac2400>, /* WKUP */ > + <0x45100000 0x00 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ > + <0x46000000 0x00 0x46000000 0x00200000>, /* CPSW */ > + <0x47000000 0x00 0x47000000 0x00068400>; /* OSPI space 1 */ > You might need #address-cells and #size-cells as 2 in MCU as well.. Could you refer to response from Vignesh? https://marc.info/?l=linux-arm-kernel&m=153572924921895&w=2 -- Regards, Nishanth Menon
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 569618b411f0..fbd6fab8dd5e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -8,13 +8,13 @@ &cbass_main { gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x01800000 0x10000>, /* GICD */ - <0x01880000 0x90000>; /* GICR */ + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0x90000>; /* GICR */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt @@ -23,7 +23,7 @@ gic_its: gic-its@18200000 { compatible = "arm,gic-v3-its"; - reg = <0x01820000 0x10000>; + reg = <0x00 0x01820000 0x00 0x10000>; msi-controller; #msi-cells = <1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 17a053552852..5d1eb877e128 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -54,31 +54,31 @@ cbass_main: interconnect@100000 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ - <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ - <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ - <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ - <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ /* MCUSS Range */ - <0x28380000 0x00 0x28380000 0x03880000>, - <0x40200000 0x00 0x40200000 0x00900100>, - <0x42040000 0x00 0x42040000 0x03ac2400>, - <0x45100000 0x00 0x45100000 0x00c24000>, - <0x46000000 0x00 0x46000000 0x00200000>, - <0x47000000 0x00 0x47000000 0x00068400>; + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, + <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; cbass_mcu: interconnect@28380000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ - <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ - <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ - <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x46000000 0x46000000 0x00200000>, /* CPSW */ - <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + ranges = <0x28380000 0x00 0x28380000 0x03880000>, /* MCU NAVSS*/ + <0x40200000 0x00 0x40200000 0x00900100>, /* First peripheral window */ + <0x42040000 0x00 0x42040000 0x03ac2400>, /* WKUP */ + <0x45100000 0x00 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x46000000 0x00 0x46000000 0x00200000>, /* CPSW */ + <0x47000000 0x00 0x47000000 0x00068400>; /* OSPI space 1 */ cbass_wakeup: interconnect@42040000 { compatible = "simple-bus";
AM65 has two PCIe controllers and each PCIe controller has '2' address spaces one within the 4GB address space of the SoC and the other above the 4GB address space of the SoC in addition to the register space. The size of the address space above the 4GB SoC address space is 4GB. These address ranges will be used by CPU/DMA to access the PCIe address space. In order to represent the address space above the 4GB SoC address space and to represent the size of this address space as 4GB, change address-cells and size-cells of interconnect to 2. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 10 +++---- arch/arm64/boot/dts/ti/k3-am65.dtsi | 38 ++++++++++++------------ 2 files changed, 24 insertions(+), 24 deletions(-) -- 2.18.0