Message ID | 1392480444-25565-22-git-send-email-peter.maydell@linaro.org |
---|---|
State | Superseded |
Headers | show |
On 17 February 2014 00:17, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >> Implement the DAIF system register which is a view of the >> DAIF bits in PSTATE. >> >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> >> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> >> --- >> target-arm/helper.c | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 367fbbe..c50ca5a 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -1589,6 +1589,25 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, >> vfp_set_fpsr(env, value); >> } >> >> +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) >> +{ >> + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { >> + return CP_ACCESS_TRAP; >> + } >> + return CP_ACCESS_OK; >> +} >> + >> +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri) >> +{ >> + return env->daif; >> +} > > Is it better to just define the .fieldoffset and do away with the > default-behaving read handler? My understanding is this will avoid a > call out to helper context when running under TCG as well, leading to > a slight perf increase. Yeah; I think this was just a holdover from when it was reading from pstate and so had to mask out the other bits. thanks -- PMM
On 17 February 2014 00:17, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >> Implement the DAIF system register which is a view of the >> DAIF bits in PSTATE. >> +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri) >> +{ >> + return env->daif; >> +} > > Is it better to just define the .fieldoffset and do away with the > default-behaving read handler? My understanding is this will avoid a > call out to helper context when running under TCG as well, leading to > a slight perf increase. I've just remembered why I didn't do this : env->daif is 32 bits, which means you can't use it as a fieldoffset for a 64 bit sysreg. thanks -- PMM
On Fri, Feb 28, 2014 at 11:48 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > On 17 February 2014 00:17, Peter Crosthwaite > <peter.crosthwaite@xilinx.com> wrote: >> On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >>> Implement the DAIF system register which is a view of the >>> DAIF bits in PSTATE. > >>> +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri) >>> +{ >>> + return env->daif; >>> +} >> >> Is it better to just define the .fieldoffset and do away with the >> default-behaving read handler? My understanding is this will avoid a >> call out to helper context when running under TCG as well, leading to >> a slight perf increase. > > I've just remembered why I didn't do this : env->daif is 32 bits, > which means you can't use it as a fieldoffset for a 64 bit sysreg. > Should env->daif just be extended to 64b then? Regards, Peter > thanks > -- PMM >
diff --git a/target-arm/helper.c b/target-arm/helper.c index 367fbbe..c50ca5a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1589,6 +1589,25 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, vfp_set_fpsr(env, value); } +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->daif; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif = value & PSTATE_DAIF; +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -1632,6 +1651,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .type = ARM_CP_NO_MIGRATE, + .access = PL0_RW, .accessfn = aa64_daif_access, + .readfn = aa64_daif_read, .writefn = aa64_daif_write }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },